Datasheet

Enhanced Capture Timer
Timer Register Descriptions
MC68HC912DT128A — Rev 4.0 Technical Data
MOTOROLA Enhanced Capture Timer 273
PBOVF — Pulse Accumulator B Overflow Flag
This bit is set when the 16-bit pulse accumulator B overflows from
$FFFF to $0000, or when 8-bit pulse accumulator 1 (PAC1) overflows
from $FF to $00.
This bit is cleared by a write to the PBFLG register with bit 1 set.
Any access to the PACN1 and PACN0 registers will clear the PBOVF
flag in this register when TFFCA bit in register TSCR($86) is set.
Read: any time
Write: has no effect.
These registers are used to latch the value of the corresponding pulse
accumulator when the related bits in register ICPAR ($A8) are enabled
(see Pulse Accumulators).
Read or write any time.
A full access for the counter register should take place in one clock cycle.
A separate read/write for high byte and low byte will give different result
than accessing them as a word.
If the RDMCL bit in MCCTL register is cleared, reads of the MCCNT
register will return the present value of the count register. If the RDMCL
PA3H–PA0H — 8-Bit Pulse Accumulators Holding Registers $00B2–$00B5
BIT 7 6 5 4 3 2 1 BIT 0
$00B2 BIt 7 6 5 4 3 2 1 Bit 0 PA3H
$00B3 Bit 7 6 5 4 3 2 1 Bit 0 PA2H
$00B4 BIt 7 6 5 4 3 2 1 Bit 0 PA1H
$00B5 Bit 7 6 5 4 3 2 1 Bit 0 PA0H
RESET: 0 0 0 0 0 0 0 0
MCCNT — Modulus Down-Counter Count Register $00B6, $00B7
BIT 7 6 5 4 3 2 1 BIT 0
$00B6 BIt 15 14 13 12 11 10 9 Bit 8 MCCNTH
$00B7 Bit 7 6 5 4 3 2 1 Bit 0 MCCNTL
RESET: 1 1 1 1 1 1 1 1
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