Datasheet

Inter IC Bus
Technical Data MC68HC912DT128A — Rev 4.0
312 Inter IC Bus MOTOROLA
Read and write anytime
IBEN — IIC Bus Enable
This bit controls the software reset of the entire IIC module.
0 = The module is reset and disabled. This is the power-on reset
situation. When low the IIC system is held in reset but registers
can still be accessed.
1 = The IIC system is enabled. This bit must be set before any other
IBCR bits have any effect.
If the IIC module is enabled in the middle of a byte transfer the
interface behaves as follows: slave mode ignores the current transfer
on the bus and starts operating whenever a subsequent start
condition is detected. Master mode will not be aware that the bus is
busy, hence if a start cycle is initiated then the current bus cycle may
become corrupt. This would ultimately result in either the current bus
master or the IIC module losing arbitration, after which bus operation
would return to normal.
NOTE: To prevent glitches from appearing on the SDA & SCL lines during reset
of the IIC module, set PORTIB bit 6 & 7 to 1 before clearing the IBEN bit.
1B 128 17 3B 2048 257
1C 144 25 3C 2304 385
1D 160 25 3D 2560 385
1E 192 33 3E 3072 513
1F 240 33 3F 3840 513
Table 17-2. IIC Divider and SDA Hold values
IBC5-0
(hex)
SCL Divider
(clocks)
SDA Hold
(clocks)
IBC5-0
(hex)
SCL Divider
(clocks)
SDA Hold
(clocks)
IBCR — IIC Bus Control Register $00E2
Bit 7654321Bit 0
IBEN IBIE MS/SL
Tx/Rx TXAK RSTA 0 IBSWAI
RESET: 00000000
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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