Datasheet

Chapter 6 Parallel Input/Output Control
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor 49
76543210
R
00
PTASE5 PTASE4 PTASE3
0
PTASE1 PTASE0
W
Reset:00111011
Figure 6-6. Slew Rate Enable for Port A Register (PTASE)
Table 6-5. PTASE Register Field Descriptions
Field Description
5:3;1:0
PTASE[5:3;1:0]
Output Slew Rate Enable for Port A Bits — Each of these control bits determines whether the output slew
rate control is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.