Datasheet

Chapter 3 Electrical Characteristics and Timing Specifications
MC9S08AC128 Series Data Sheet, Rev. 4
28 Freescale Semiconductor
Figure 3-11. Active Background Debug Mode Latch Timing
Figure 3-12. IRQ/KBIPx Timing
3.10.2 Timer/PWM (TPM) Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the
optional external source to the timer counter. These synchronizers operate from the current bus rate clock.
Table 3-13. TPM Input Timing
Function Symbol Min Max Unit
External clock frequency
f
TPMext
dc
f
Bus
/4
MHz
External clock period
t
TPMext
4—
t
cyc
External clock high time
t
clkh
1.5 —
t
cyc
External clock low time
t
clkl
1.5 —
t
cyc
Input capture pulse width
t
ICPW
1.5 —
t
cyc
BKGD/MS
RESET
t
MSSU
t
MSH
t
IHIL
IRQ/KBIP7-KBIP4
t
ILIH
IRQ/KBIPx