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HCS08

Microcontrollers

freescale.com

MC9S08AC16

MC9S08AC8

MC9S08AW16A

MC9S08AW8A

Data Sheet

MC9S08AC16

Rev. 9

8/2011

Summary of content (337 pages)

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MC9S08AC16 MC9S08AC8 MC9S08AW16A MC9S08AW8A Data Sheet HCS08 Microcontrollers MC9S08AC16 Rev. 9 8/2011 freescale.
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MC9S08AC16 Series Features MC9S08AC16 Series Devices • • Consumer & Industrial — MC9S08AC16 — MC9S08AC8 Automotive — MC9S08AW16A — MC9S08AW8A Peripherals • • • • 8-Bit HCS08 Central Processor Unit (CPU) • • • • • • • 40-MHz HCS08 CPU (central processor unit) 20-MHz internal bus frequency HC08 instruction set with added BGND instruction Background debugging system Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) De
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MC9S08AC16 Series Data Sheet Covers MC9S08AC16 MC9S08AC8 MC9S08AW16A MC9S08AW8A MC9S08AC16 Rev.
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Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision Number Revision Date 0 12/2007 Initial Release.
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List of Chapters Chapter Title Page Chapter 1 Introduction.............................................................................. 19 Chapter 2 Pins and Connections ............................................................. 25 Chapter 3 Modes of Operation ................................................................. 35 Chapter 4 Memory ..................................................................................... 41 Chapter 5 Resets, Interrupts, and System Configuration .....
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Contents Section Number Title Page Chapter 1 Introduction 1.1 1.2 1.3 Overview .........................................................................................................................................19 MCU Block Diagrams .....................................................................................................................20 System Clock Distribution ..............................................................................................................
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Section Number 4.2 4.3 4.4 4.5 4.6 Title Page Register Addresses and Bit Assignments ........................................................................................43 RAM ................................................................................................................................................49 FLASH ............................................................................................................................................50 4.4.1 Features .................
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Section Number 5.9.6 5.9.7 5.9.8 5.9.9 5.9.10 Title Page System Device Identification Register (SDIDH, SDIDL) ................................................75 System Real-Time Interrupt Status and Control Register (SRTISC) ................................76 System Power Management Status and Control 1 Register (SPMSC1) ...........................77 System Power Management Status and Control 2 Register (SPMSC2) ...........................79 System Options Register 2 (SOPT2) .............................
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Section Number Title Page Chapter 7 Central Processor Unit (S08CPUV2) 7.1 7.2 7.3 7.4 7.5 Introduction ...................................................................................................................................107 7.1.1 Features ...........................................................................................................................107 Programmer’s Model and CPU Registers .....................................................................................
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Section Number 8.4 8.5 Title Page 8.3.6 ICG Trim Register (ICGTRM) ........................................................................................137 Functional Description ..................................................................................................................137 8.4.1 Off Mode (Off) ................................................................................................................138 8.4.2 Self-Clocked Mode (SCM) .........................................
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Section Number 10.4 10.5 10.6 10.7 10.8 10.9 Title Page 10.3.3 Modes of Operation ........................................................................................................164 10.3.4 Block Diagram ................................................................................................................165 Signal Description .........................................................................................................................167 10.4.
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Section Number Title Page Chapter 12 Serial Peripheral Interface (S08SPIV3) 12.1 Introduction ...................................................................................................................................209 12.1.1 Features ...........................................................................................................................211 12.1.2 Block Diagrams ..............................................................................................................
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Section Number Title Page 13.4.2 10-bit Address .................................................................................................................238 13.4.3 General Call Address ......................................................................................................239 13.5 Resets ............................................................................................................................................239 13.6 Interrupts ......................................
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Section Number Title Page 14.5.7 MCU Stop3 Mode Operation ..........................................................................................262 14.5.8 MCU Stop1 and Stop2 Mode Operation .........................................................................263 14.6 Initialization Information ..............................................................................................................263 14.6.1 ADC Module Initialization Example ...................................................
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Section Number Title Page A.10.1 Control Timing ................................................................................................................311 A.10.2 Timer/PWM (TPM) Module Timing ...............................................................................312 A.11 SPI Characteristics .........................................................................................................................314 A.12 FLASH Specifications..................................................
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Chapter 1 Introduction 1.1 Overview The MC9S08AC16 Series devices are members of the low-cost, high-performance HCS08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available with a variety of modules, memory sizes, memory types, and package types. Refer to Table 1-1 for memory sizes and package types. • • NOTE The MC9S08AC16 and MC9S08AC8 devices are qualified for, and are intended to be used in, consumer and industrial applications.
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Chapter 1 Introduction Table 1-1.
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10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC1) HCS08 CORE IRQ/TPMCLK CPU PTA7 PTA2 PTA1 PTA0 PTB3/AD1P3 PTB2/AD1P2 PTB1/TPM3CH1/AD1P1 PTB0/TPM3CH0/AD1P0 SDA1 IIC MODULE (IIC1) SCL1 INTERNAL CLOCK GENERATOR (ICG) EXTAL XTAL HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT PORT C RESET 4 AD1P11–AD1P8 DEBUG MODULE (DBG) BKGD/MS BDC 4 AD1P3–AD1P0 PORT A VDDAD VSSAD VREFL VREFH PORT B Chapter 1 Introduction PTC5/RxD2 PTC4 PTC3/TxD2 PTC2/MCLK PTC1/SDA1 PTC0/SCL1 TPMCL
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Chapter 1 Introduction Table 1-2 lists the functional versions of the on-chip modules. Table 1-2. Versions of On-Chip Modules Module 1.
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Chapter 1 Introduction • • • — Control bits inside the ICG determine which source is connected. FFE is a control signal generated inside the ICG. If the frequency of ICGOUT > 4  the frequency of ICGERCLK, this signal is a logic 1 and the fixed-frequency clock will be ICGERCLK/2. Otherwise the fixed-frequency clock will be BUSCLK. ICGLCLK — Development tools can select this internal self-clocked source (~ 8 MHz) to speed up BDC communications in systems where the bus clock is slow.
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Chapter 1 Introduction MC9S08AC16 Series Data Sheet, Rev.
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Chapter 2 Pins and Connections 2.1 Introduction This chapter describes signals that connect to package pins. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. 2.2 Device Pin Assignment 37 PTG4/KB1IP4 38 VREFH 39 VREFL 40 BKGD/MS 41 PTG5/XTAL 42 PTG6/EXTAL PTC4 1 43 VSS 44 PTC0/SCL1 45 PTC1/SDA1 46 PTC2/MCLK 47 PTC3/TxD2 48 PTC5/RxD2 Figure 2-1 shows the 48-pin QFN pin assignments for the MC9S08AC16 Series device.
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Chapter 2 Pins and Connections PTC2/MCLK PTC1/SDA1 PTC0/SCL1 VSS PTG6/EXTAL PTG5/XTAL BKGD/MS VREFL 43 42 41 40 39 38 37 36 35 34 44 PTC4 1 VREFH PTC3/TxD2 PTC5/RxD2 Figure 2-2. shows the 44-pin LQFP pin assignments for the MC9S08AC16 Series device.
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Chapter 2 Pins and Connections Figure 2-3 shows the 42-pin SDIP pin assignments for the MC9S08AC16 Series device.
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Chapter 2 Pins and Connections PTC0/SCL1 VSS PTG6/EXTAL PTG5/XTAL BKGD/MS VREFL VREFH PTC1/SDA1 Figure 2-4 shows the 32-pin LQFP pin assignments for the MC9S08AC16 Series device.
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Chapter 2 Pins and Connections Table 2-1.
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Chapter 2 Pins and Connections 2.3 Recommended System Connections Figure 2-5 shows pin connections that are common to almost all MC9S08AC16 Series application systems. MC9S08AC16 Series Data Sheet, Rev.
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Chapter 2 Pins and Connections VREFH CBYAD 0.1 F PTA0 VSSAD VREFL VDD VDD SYSTEM POWER + 5V MC9S08AC16 VDDAD CBLK + 10 F PORT A CBY 0.
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Chapter 2 Pins and Connections 2.3.1 Power (VDD, 2 x VSS, VDDAD, VSSAD) VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides regulated lower-voltage source to the CPU and other internal circuitry of the MCU. Typically, application systems have two separate capacitors across the power pins.
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Chapter 2 Pins and Connections external reset circuitry unnecessary. This pin is normally connected to the standard 6-pin background debug connector so a development system can directly reset the MCU system. If desired, a manual external reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset). Whenever any reset is initiated (whether from an external signal or from an internal system), the reset pin is driven low for approximately 34 bus cycles.
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Chapter 2 Pins and Connections 2.3.7 General-Purpose I/O and Peripheral Ports The remaining pins are shared among general-purpose I/O and on-chip peripheral functions such as timers and serial I/O systems. Immediately after reset, all of these pins are configured as high-impedance general-purpose inputs with internal pullup devices disabled.
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Chapter 3 Modes of Operation 3.1 Introduction The operating modes of the MC9S08AC16 Series are described in this chapter. Entry into each mode, exit from each mode, and functionality while in each of the modes are described. 3.2 • • • 3.
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Chapter 3 Modes of Operation After entering active background mode, the CPU is held in a suspended state waiting for serial background commands rather than executing instructions from the user’s application program. Background commands are of two types: • Non-intrusive commands, defined as commands that can be issued while the user program is running.
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Chapter 3 Modes of Operation the CPU executes a STOP instruction, the MCU will not enter either of the stop modes and an illegal opcode reset is forced. The stop modes are selected by setting the appropriate bits in SPMSC2. HCS08 devices that are designed for low voltage operation (1.8V to 3.6V) also include stop1 mode. The MC9S08AC16 Series family of devices does not include stop1 mode. Table 3-1 summarizes the behavior of the MCU in each of the stop modes. Table 3-1.
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Chapter 3 Modes of Operation register bits will assume their reset states when the I/O pin latches are opened and the I/O pins will switch to their reset states. For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O latches are opened. 3.6.
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Chapter 3 Modes of Operation Table 3-2. BDM Enabled Stop Mode Behavior Mode PPDC CPU, Digital Peripherals, FLASH RAM ICG ADC Regulator I/O Pins RTI Stop3 0 Standby Standby Active Optionally on Active States held Optionally on 3.6.4 LVD Enabled in Stop Mode The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below the LVD voltage.
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Chapter 3 Modes of Operation TPM — When the MCU enters stop mode, the clock to the TPM1 and TPM2 modules stop. The modules halt operation. If the MCU is configured to go into stop2 mode, the TPM modules will be reset upon wake-up from stop and must be reinitialized. ADC — When the MCU enters stop mode, the ADC will enter a low-power standby state unless the asynchronous clock source, ADACK, is enabled. Conversions can occur in stop3 if ADACK is enabled.
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Chapter 4 Memory 4.1 MC9S08AC16 Series Memory Map Figure 4-1 shows the memory maps for the MC9S08AC16 Series MCUs. On-chip memory in the MC9S08AC16 Series of MCU consists of RAM, FLASH program memory for nonvolatile data storage, plus I/O and control/status registers.
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Chapter 4 Memory 4.1.1 Reset and Interrupt Vector Assignments Figure 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the Freescale-provided equate file for the MC9S08AC16 Series. For more details about resets, interrupts, interrupt priority, and local interrupt mask controls, refer to Chapter 5, “Resets, Interrupts, and System Configuration.” Table 4-1.
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Chapter 4 Memory 4.2 Register Addresses and Bit Assignments The registers in the MC9S08AC16 Series are divided into these three groups: • Direct-page registers are located in the first 112 locations in the memory map, so they are accessible with efficient direct addressing mode instructions. • High-page registers are used much less often, so they are located above 0x1800 in the memory map. This leaves more room in the direct page for more frequently used registers and variables.
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Chapter 4 Memory Table 4-2.
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Chapter 4 Memory Table 4-2.
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Chapter 4 Memory Table 4-2.
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Chapter 4 Memory Table 4-3.
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Chapter 4 Memory Table 4-3.
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Chapter 4 Memory Table 4-4.
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Chapter 4 Memory When security is enabled, the RAM is considered a secure memory resource and is not accessible through BDM or through code executing from non-secure memory. See Section 4.5, “Security” for a detailed description of the security feature. 4.4 FLASH The FLASH memory is intended primarily for program storage. In-circuit programming allows the operating program to be loaded into the FLASH memory after final assembly of the application product.
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Chapter 4 Memory Table 4-5. Program and Erase Times Parameter Cycles of FCLK Time if FCLK = 200 kHz Byte program 9 45 s Byte program (burst) 4 20 s1 Page erase 4000 20 ms Mass erase 20,000 100 ms 1 4.4.3 Excluding start/end overhead Program and Erase Command Execution The steps for executing any of the commands are listed below. The FCDIV register must be initialized and any error flags cleared before beginning command execution. The command execution steps are: 1.
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Chapter 4 Memory burst programming. The FCDIV register must be initialized before using any FLASH commands. This only must be done once following a reset. WRITE TO FCDIV (Note 1) FLASH PROGRAM AND ERASE FLOW Note 1: Required only once after reset. START FACCERR ? 0 1 CLEAR ERROR WRITE TO FLASH TO BUFFER ADDRESS AND DATA WRITE COMMAND TO FCMD WRITE 1 TO FCBEF TO LAUNCH COMMAND AND CLEAR FCBEF (Note 2) FPVIOL OR FACCERR ? Note 2: Wait at least four bus cycles before checking FCBEF or FCCF.
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Chapter 4 Memory • The next sequential address selects a byte on the same physical row as the current byte being programmed. A row of FLASH memory consists of 64 bytes. A byte within a row is selected by addresses A5 through A0. A new row begins when addresses A5 through A0 are all zero. The first byte of a series of sequential bytes being programmed in burst mode will take the same amount of time to program as a byte programmed in standard mode.
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Chapter 4 Memory 4.4.5 Access Errors An access error occurs whenever the command execution protocol is violated. Any of the following specific actions will cause the access error flag (FACCERR) in FSTAT to be set. FACCERR must be cleared by writing a 1 to FACCERR in FSTAT before any command can be processed.
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Chapter 4 Memory memory. In addition to programming the FPS bits to the appropriate value, FPDIS (bit 0 of NVPROT) must be programmed to logic 0 to enable block protection. Therefore the value 0xF8 must be programmed into NVPROT to protect addresses 0xFA00 through 0xFFFF. FPS7 FPS6 FPS5 FPS4 FPS3 A15 A14 A13 A12 A11 FPS2 FPS1 A10 A9 1 1 1 1 1 1 1 1 1 A8 A7 A6 A5 A4 A3 A2 A1 A0 Figure 4-4.
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Chapter 4 Memory disengages security and the other three combinations engage security. Notice the erased state (1:1) makes the MCU secure. During development, whenever the FLASH is erased, it is good practice to immediately program the SEC00 bit to 0 in NVOPT so SEC01:SEC00 = 1:0. This would allow the MCU to remain unsecured after a subsequent reset. The on-chip debug module cannot be enabled while the MCU is secure.
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Chapter 4 Memory 4.6 FLASH Registers and Control Bits The FLASH module has nine 8-bit registers in the high-page register space, three locations in the nonvolatile register space in FLASH memory which are copied into three corresponding high-page control registers at reset. There is also an 8-byte comparison key in FLASH memory. Refer to Table 4-3 and Table 4-4 for the absolute address assignments for all FLASH registers. This section refers to registers and control bits only by their names.
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Chapter 4 Memory Table 4-7. FLASH Clock Divider Settings 4.6.2 fBus PRDIV8 (Binary) DIV5:DIV0 (Decimal) fFCLK Program/Erase Timing Pulse (5 s Min, 6.7s Max) 20 MHz 1 12 192.3 kHz 5.2 s 10 MHz 0 49 200 kHz 5 s 8 MHz 0 39 200 kHz 5 s 4 MHz 0 19 200 kHz 5 s 2 MHz 0 9 200 kHz 5 s 1 MHz 0 4 200 kHz 5 s 200 kHz 0 0 200 kHz 5 s 150 kHz 0 0 150 kHz 6.
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Chapter 4 Memory Table 4-9. Security States SEC01:SEC00 Description 0:0 secure 0:1 secure 1:0 unsecured 1:1 secure SEC01:SEC00 changes to 1:0 after successful backdoor key entry or a successful blank check of FLASH. 4.6.3 FLASH Configuration Register (FCNFG) Bits 7 through 5 may be read or written at any time. Bits 4 through 0 always read 0 and cannot be written. R 7 6 0 0 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 KEYACC W Reset 0 0 0 = Unimplemented or Reserved Figure 4-7.
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Chapter 4 Memory 4.6.4 FLASH Protection Register (FPROT and NVPROT) During reset, the contents of the nonvolatile location NVPROT are copied from FLASH into FPROT. This register can be read at any time. If FPDIS = 0, protection can be increased, i.e., a smaller value of FPS can be written. If FPDIS = 1, writes do not change protection. 7 6 5 R 4 3 2 1 FPS1 0 FPDIS1 W Reset This register is loaded from nonvolatile location NVPROT during reset.
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Chapter 4 Memory Table 4-12. FSTAT Register Field Descriptions Field Description 7 FCBEF FLASH Command Buffer Empty Flag — The FCBEF bit is used to launch commands. It also indicates that the command buffer is empty so that a new command sequence can be executed when performing burst programming. The FCBEF bit is cleared by writing a one to it or when a burst program command is transferred to the array for programming. Only burst program commands can be buffered.
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Chapter 4 Memory Table 4-13. FCMD Register Field Descriptions Field 7:0 FCMD[7:0] Description FLASH Command Bits — See Table 4-14 Table 4-14. FLASH Commands Command FCMD Equate File Label Blank check 0x05 mBlank Byte program 0x20 mByteProg Byte program — burst mode 0x25 mBurstProg Page erase (512 bytes/page) 0x40 mPageErase Mass erase (all FLASH) 0x41 mMassErase All other command codes are illegal and generate an access error.
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Chapter 5 Resets, Interrupts, and System Configuration 5.1 Introduction This chapter discusses basic reset and interrupt mechanisms and the various sources of reset and interrupts in the MC9S08AC16 Series. Some interrupt sources from peripheral modules are discussed in greater detail within other chapters of this data manual. This chapter gathers basic information about all reset and interrupt sources in one place for easy reference.
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Chapter 5 Resets, Interrupts, and System Configuration • • • • • • Computer operating properly (COP) timer Illegal opcode detect Illegal address detect Background debug forced reset The reset pin (RESET) Clock generator loss of lock and loss of clock reset Each of these sources, with the exception of the background debug forced reset, has an associated bit in the system reset status register. 5.
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Chapter 5 Resets, Interrupts, and System Configuration The write to SRS that services (clears) the COP counter must not be placed in an interrupt service routine (ISR) because the ISR could continue to be executed periodically even if the main application program fails. In background debug mode, the COP counter will not increment. When the bus clock source is selected, the COP counter does not increment while the system is in stop mode. The COP counter resumes as soon as the MCU exits stop mode.
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Chapter 5 Resets, Interrupts, and System Configuration NOTE For compatibility with the M68HC08, the H register is not automatically saved and restored. It is good programming practice to push H onto the stack at the start of the interrupt service routine (ISR) and restore it immediately before the RTI that is used to return from the ISR. When two or more interrupts are pending when the I bit is cleared, the highest priority source is serviced first (see Table 5-2). 5.5.
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Chapter 5 Resets, Interrupts, and System Configuration stop mode and system clocks are shut down, a separate asynchronous path is used so the IRQ (if enabled) can wake the MCU. 5.5.2.1 IRQ Pin Configuration Options The IRQ pin enable (IRQPE) control bit in IRQSC must be 1 in order for the IRQ pin to act as the interrupt request (IRQ) input.
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Chapter 5 Resets, Interrupts, and System Configuration Table 5-2. Vector Summary Vector Priority Vector No.
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Chapter 5 Resets, Interrupts, and System Configuration 5.6 Low-Voltage Detect (LVD) System The MC9S08AC16 Series includes a system to protect against low voltage conditions in order to protect memory contents and control MCU system states during supply voltage variations. The system is comprised of a power-on reset (POR) circuit and an LVD circuit with a user selectable trip voltage, either high (VLVDH) or low (VLVDL).
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Chapter 5 Resets, Interrupts, and System Configuration Either RTI clock source can be used when the MCU is in run, wait or stop3 mode. When using the external oscillator in stop3, it must be enabled in stop (OSCSTEN = 1) and configured for low bandwidth operation (RANGE = 0). Only the internal 1-kHz clock source can be selected to wake the MCU from stop2 mode.
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Chapter 5 Resets, Interrupts, and System Configuration 5.9.1 Interrupt Pin Request Status and Control Register (IRQSC) This direct page register includes status and control bits which are used to configure the IRQ function, report status, and acknowledge IRQ events. 7 R 6 5 4 IRQPDD IRQEDG IRQPE 0 3 2 IRQF 0 W Reset 1 0 IRQIE IRQMOD 0 0 IRQACK 0 0 0 0 0 0 = Unimplemented or Reserved Figure 5-2. Interrupt Request Status and Control Register (IRQSC) Table 5-3.
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Chapter 5 Resets, Interrupts, and System Configuration 5.9.2 System Reset Status Register (SRS) This register includes seven read-only status flags to indicate the source of the most recent reset. When a debug host forces reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS will be set. Writing any value to this register address clears the COP watchdog timer without affecting the contents of this register. The reset state of these bits depends on what caused the MCU to reset.
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Chapter 5 Resets, Interrupts, and System Configuration Table 5-4. SRS Register Field Descriptions (continued) Field Description 3 ILAD Illegal Address — Reset was caused by an attempt to access a designated illegal address. 0 Reset not caused by an illegal address access. 1 Reset caused by an illegal address access.
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Chapter 5 Resets, Interrupts, and System Configuration 5.9.4 System Options Register (SOPT) This register may be read at any time. Bits 3 and 2 are unimplemented and always read 0. This is a write-once register so only the first write after reset is honored. Any subsequent attempt to write to SOPT (intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings.
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Chapter 5 Resets, Interrupts, and System Configuration 5.9.5 System MCLK Control Register (SMCLK) This register is used to control the MCLK clock output. R 7 6 5 0 0 0 4 3 2 1 0 0 MPE MCSEL W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 5-6. System MCLK Control Register (SMCLK) Table 5-7. SMCLK Register Field Descriptions Field 4 MPE 2:0 MCSEL Description MCLK Pin Enable — This bit is used to enable the MCLK function. 0 MCLK output disabled.
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Chapter 5 Resets, Interrupts, and System Configuration R 7 6 5 4 3 2 1 0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0 0 0 1 0 0 1 0 W Reset = Unimplemented or Reserved Figure 5-8. System Device Identification Register — Low (SDIDL) Table 5-9. SDIDL Register Field Descriptions Field 7:0 ID[7:0] 5.9.7 Description Part Identification Number — Each derivative in the HCS08 Family has a unique identification number. The MC9S08AC16 Series is hard coded to the value 0x012.
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Chapter 5 Resets, Interrupts, and System Configuration Table 5-11. Real-Time Interrupt Frequency 1 RTIS2:RTIS1:RTIS0 1-kHz Clock Source Delay1 Using External Clock Source Delay (Crystal Frequency) 0:0:0 Disable periodic wakeup timer Disable periodic wakeup timer 0:0:1 8 ms divide by 256 0:1:0 32 ms divide by 1024 0:1:1 64 ms divide by 2048 1:0:0 128 ms divide by 4096 1:0:1 256 ms divide by 8192 1:1:0 512 ms divide by 16384 1:1:1 1.
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Chapter 5 Resets, Interrupts, and System Configuration Table 5-12. SPMSC1 Register Field Descriptions (continued) Field Description 3 LVDSE Low-Voltage Detect Stop Enable — Provided LVDE = 1, this read/write bit determines whether the low-voltage detect function operates when the MCU is in stop mode. 0 Low-voltage detect disabled during stop mode. 1 Low-voltage detect enabled during stop mode.
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Chapter 5 Resets, Interrupts, and System Configuration 5.9.9 System Power Management Status and Control 2 Register (SPMSC2) This register is used to report the status of the low voltage warning function, and to configure the stop mode behavior of the MCU.
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Chapter 5 Resets, Interrupts, and System Configuration 5.9.10 System Options Register 2 (SOPT2) This high page register contains bits to configure MCU specific features on the MC9S08AC16 Series devices. 7 R COPCLKS1 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset: 1 = Unimplemented or Reserved 1 This bit can be written only one time after reset. Additional writes are ignored. Figure 5-12. System Options Register 2 (SOPT2) Table 5-14.
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Chapter 6 Parallel Input/Output 6.1 Introduction This chapter explains software controls related to parallel input/output (I/O). The MC9S08AC16 has seven I/O ports which include a total of 38 general-purpose I/O pins. See Chapter 2, “Pins and Connections” for more information about the logic and hardware aspects of these pins. Many of these pins are shared with on-chip peripherals such as timer systems, communication systems, or keyboard interrupts.
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10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC1) HCS08 CORE IRQ/TPMCLK CPU PTA7 PTA2 PTA1 PTA0 PTB3/AD1P3 PTB2/AD1P2 PTB1/TPM3CH1/AD1P1 PTB0/TPM3CH0/AD1P0 SDA1 IIC MODULE (IIC1) SCL1 INTERNAL CLOCK GENERATOR (ICG) EXTAL XTAL HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT PTC5/RxD2 PTC4 PTC3/TxD2 PTC2/MCLK PTC1/SDA1 PTC0/SCL1 PORT C RESET 4 AD1P11–AD1P8 DEBUG MODULE (DBG) BKGD/MS BDC 4 AD1P3–AD1P0 PORT A VDDAD VSSAD VREFL VREFH PORT B Chapter 6 Parallel Input/Outp
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Chapter 6 Parallel Input/Output 6.
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Chapter 6 Parallel Input/Output 6.3.2 Port B Port B Bit 7 6 5 4 R R R R 3 MCU Pin: 2 PTB3/ PTB2/ TPM3CH0/ TPM3CH1/ AD1P3 AD1P2 1 Bit 0 PTB1/ AD1P1 PTB0/ AD1P0 Figure 6-3. Port B Pin Names Port B pins are general-purpose I/O pins. Parallel I/O function is controlled by the port B data (PTBD) and data direction (PTBDD) registers which are located in page zero register space.
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Chapter 6 Parallel Input/Output 6.3.4 Port D Port D Bit 7 6 5 4 R R R R MCU Pin: 3 2 PTD3/ PTD2/ AD1P11/ AD1P10/ KBIP6 KBIP5 1 Bit 0 PTD1/ AD1P9 PTD0/ AD1P8 Figure 6-5. Port D Pin Names Port D pins are general-purpose I/O pins. Parallel I/O function is controlled by the port D data (PTDD) and data direction (PTDDD) registers which are located in page zero register space.
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Chapter 6 Parallel Input/Output Refer to Chapter 11, “Serial Communications Interface (S08SCIV4)” for more information about using port E pins as SCI pins. Refer to Chapter 12, “Serial Peripheral Interface (S08SPIV3)” for more information about using port E pins as SPI pins. Refer to Chapter 10, “Timer/PWM (S08TPMV3)” for more information about using port E pins as TPM channel pins. 6.3.
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Chapter 6 Parallel Input/Output Refer to Chapter 8, “Internal Clock Generator (S08ICGV4)” for more information about using port G pins as XTAL and EXTAL pins. Refer to Chapter 9, “Keyboard Interrupt (S08KBIV1)” for more information about using port G pins as keyboard inputs. 6.4 Parallel I/O Control Reading and writing of parallel I/O is done through the port data registers. The direction, input or output, is controlled through the port data direction registers.
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Chapter 6 Parallel Input/Output has priority such that if both the digital and analog functions are enabled, the analog function controls the pin. It is a good programming practice to write to the port data register before changing the direction of a port pin to become an output. This ensures that the pin will not be driven momentarily with an old data value that happened to be in the port data register. 6.5 Pin Control The pin control registers are located in the high page register block of the memory.
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Chapter 6 Parallel Input/Output 6.6 Pin Behavior in Stop Modes Depending on the stop mode, I/O functions differently as the result of executing a STOP instruction. An explanation of I/O behavior for the various stop modes follows: • Stop2 mode is a partial power-down mode, whereby I/O latches are maintained in their state as before the STOP instruction was executed.
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Chapter 6 Parallel Input/Output 7 6 5 4 3 2 1 0 PTADD7 R R R R PTADD2 PTADD1 PTADD0 0 0 0 0 0 0 0 0 R W Reset Figure 6-11. Data Direction for Port A Register (PTADD)1 1 Bits 6 through 3 are reserved bits that must always be written to 0. Table 6-2. PTADD Register Field Descriptions Field Description 7, 2:0 PTADDn Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for PTAD reads.
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Chapter 6 Parallel Input/Output 7 6 5 4 3 2 1 0 PTASE7 R R R R PTASE2 PTASE1 PTASE0 0 0 0 0 0 0 0 0 R W Reset Figure 6-13. Output Slew Rate Control Enable for Port A (PTASE)1 1 Bits 6 through 3 are reserved bits that must always be written to 0. Table 6-4. PTASE Register Field Descriptions Field Description 7, 2:0 PTASEn Output Slew Rate Control Enable for Port A Bits — Each of these control bits determine whether output slew rate control is enabled for the associated PTA pin.
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Chapter 6 Parallel Input/Output 6.7.3 Port B I/O Registers (PTBD and PTBDD) Port B parallel I/O function is controlled by the registers in this section. 7 6 5 4 3 2 1 0 R R R R PTBD3 PTBD2 PTBD1 PTBD0 0 0 0 0 0 0 0 0 R W Reset Figure 6-15. Port B Data Register (PTBD)1 1 Bits 7 through 4 are reserved bits that must always be written to 0. Table 6-6.
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Chapter 6 Parallel Input/Output 6.7.4 Port B Pin Control Registers (PTBPE, PTBSE, PTBDS) In addition to the I/O control, port B pins are controlled by the registers listed below. 7 6 5 4 3 2 1 0 R R R R PTBPE3 PTBPE2 PTBPE1 PTBPE0 0 0 0 0 0 0 0 0 R W Reset Figure 6-17. Internal Pullup Enable for Port B (PTBPE)1 1 Bits 7 through 4 are reserved bits that must always be written to 0. Table 6-8.
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Chapter 6 Parallel Input/Output 7 6 5 4 3 2 1 0 R R R R PTBDS3 PTBDS2 PTBDS1 PTBDS0 0 0 0 0 0 0 0 0 R W Reset Figure 6-19. Output Drive Strength Selection for Port B (PTBDS)1 1 Bits 7 through 4 are reserved bits that must always be written to 0. Table 6-10. PTBDS Register Field Descriptions Field Description 3:0 Output Drive Strength Selection for Port B Bits — Each of these control bits selects between low and high PTBDS[3:0] output drive for the associated PTB pin.
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Chapter 6 Parallel Input/Output 7 R 6 5 4 3 2 1 0 R PTCDD5 PTCDD4 PTCDD3 PTCDD2 PTCDD1 PTCDD0 0 0 0 0 0 0 0 0 W Reset 0 Figure 6-21. Data Direction for Port C (PTCDD)1 1 Bit 6 is a reserved bit that must always be written to 0. Table 6-12. PTCDD Register Field Descriptions Field Description 5:0 Data Direction for Port C Bits — These read/write bits control the direction of port C pins and what is read for PTCDD[5:0] PTCD reads.
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Chapter 6 Parallel Input/Output 7 R 6 5 4 3 2 1 0 R PTCSE5 PTCSE4 PTCSE3 PTCSE2 PTCSE1 PTCSE0 0 0 0 0 0 0 0 0 W Reset 0 Figure 6-23. Output Slew Rate Control Enable for Port C (PTCSE)1 1 Bit 6 is a reserved bit that must always be written to 0. Table 6-14.
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Chapter 6 Parallel Input/Output 6.7.7 Port D I/O Registers (PTDD and PTDDD) Port D parallel I/O function is controlled by the registers listed below. 7 6 5 4 3 2 1 0 R R R R PTDD3 PTDD2 PTDD1 PTDD0 0 0 0 0 0 0 0 0 R W Reset Figure 6-25. Port D Data Register (PTDD)1 1 Bits 7 through 4 are reserved bits that must always be written to 0. Table 6-16.
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Chapter 6 Parallel Input/Output 6.7.8 Port D Pin Control Registers (PTDPE, PTDSE, PTDDS) In addition to the I/O control, port D pins are controlled by the registers listed below. 7 6 5 4 3 2 1 0 R R R R PTDPE3 PTDPE2 PTDPE1 PTDPE0 0 0 0 0 0 0 0 0 R W Reset Figure 6-27. Internal Pullup Enable for Port D (PTDPE)1 1 Bits 7 through 4 are reserved bits that must always be written to 0. Table 6-18.
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Chapter 6 Parallel Input/Output 7 6 5 4 3 2 1 0 R R R R PTDDS3 PTDDS2 PTDDS1 PTDDS0 0 0 0 0 0 0 0 0 R W Reset Figure 6-29. Output Drive Strength Selection for Port D (PTDDS)1 1 Bits 7 through 4 are reserved bits that must always be written to 0. Table 6-20. PTDDS Register Field Descriptions Field Description 3:0 Output Drive Strength Selection for Port D Bits — Each of these control bits selects between low and high PTDDS[3:0] output drive for the associated PTD pin.
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Chapter 6 Parallel Input/Output 7 6 5 4 3 2 1 0 PTEDD7 PTEDD6 PTEDD5 PTEDD4 PTEDD3 PTEDD2 PTEDD1 PTEDD0 0 0 0 0 0 0 0 0 R W Reset Figure 6-31. Data Direction for Port E (PTEDD) Table 6-22. PTEDD Register Field Descriptions Field Description 7:0 Data Direction for Port E Bits — These read/write bits control the direction of port E pins and what is read for PTEDD[7:0] PTED reads. 0 Input (output driver disabled) and reads return the pin value.
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Chapter 6 Parallel Input/Output 7 6 5 4 3 2 1 0 PTESE7 PTESE6 PTESE5 PTESE4 PTESE3 PTESE2 PTESE1 PTESE0 0 0 0 0 0 0 0 0 R W Reset Figure 6-33. Output Slew Rate Control Enable for Port E (PTESE) Table 6-24. PTESE Register Field Descriptions Field Description 7:0 Output Slew Rate Control Enable for Port E Bits — Each of these control bits determine whether output slew PTESE[7:0] rate control is enabled for the associated PTE pin.
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Chapter 6 Parallel Input/Output 6.7.11 Port F I/O Registers (PTFD and PTFDD) Port F parallel I/O function is controlled by the registers listed below. 7 6 5 4 3 2 1 0 R PTFD6 PTFD5 PTFD4 R R PTFD1 PTFD0 0 0 0 0 0 0 0 0 R W Reset Figure 6-35. Port F Data Register (PTFD)1 1 Bits 7, 3 and 2 are reserved bits that must always be written to 0. Table 6-26.
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Chapter 6 Parallel Input/Output 6.7.12 Port F Pin Control Registers (PTFPE, PTFSE, PTFDS) In addition to the I/O control, port F pins are controlled by the registers listed below. 7 6 5 4 3 2 1 0 R PTFPE6 PTFPE5 PTFPE4 R R PTFPE1 PTFPE0 0 0 0 0 0 0 0 0 R W Reset Figure 6-37. Internal Pullup Enable for Port F (PTFPE)1 1 Bits 7, 3 and 2 are reserved bits that must always be written to 0. Table 6-28.
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Chapter 6 Parallel Input/Output 7 6 5 4 3 2 1 0 R PTFDS6 PTFDS5 PTFDS4 R R PTFDS1 PTFDS0 0 0 0 0 0 0 0 0 R W Reset Figure 6-39. Output Drive Strength Selection for Port F (PTFDS)1 1 Bits 7, 3 and 2 are reserved bits that must always be written to 0. Table 6-30. PTFDS Register Field Descriptions Field 6:4, 1:0 PTFDSn 6.7.
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Chapter 6 Parallel Input/Output 7 R 6 5 4 3 2 1 0 PTGDD6 PTGDD5 PTGDD4 PTGDD3 PTGDD2 PTGDD1 PTGDD0 0 0 0 0 0 0 0 0 W Reset 0 Figure 6-41. Data Direction for Port G (PTGDD) Table 6-32. PTGDD Register Field Descriptions Field Description 6:0 Data Direction for Port G Bits — These read/write bits control the direction of port G pins and what is read for PTGDD[6:0] PTGD reads. 0 Input (output driver disabled) and reads return the pin value.
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Chapter 6 Parallel Input/Output 7 R 6 5 4 3 2 1 0 PTGSE6 PTGSE5 PTGSE4 PTGSE3 PTGSE2 PTGSE1 PTGSE0 0 0 0 0 0 0 0 0 W Reset 0 Figure 6-43. Output Slew Rate Control Enable for Port G Bits (PTGSE) Table 6-34. PTGSE Register Field Descriptions Field Description 6:0 Output Slew Rate Control Enable for Port G Bits— Each of these control bits determine whether output slew PTGSE[6:0] rate control is enabled for the associated PTG pin.
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Chapter 7 Central Processor Unit (S08CPUV2) 7.1 Introduction This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU.
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Chapter 7 Central Processor Unit (S08CPUV2) 7.2 Programmer’s Model and CPU Registers Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map. 7 0 ACCUMULATOR A 16-BIT INDEX REGISTER H:X H INDEX REGISTER (HIGH) 8 15 INDEX REGISTER (LOW) 7 X 0 SP STACK POINTER 0 15 PROGRAM COUNTER 7 0 CONDITION CODE REGISTER V 1 1 H I N Z C PC CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-1. CPU Registers 7.2.
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Chapter 7 Central Processor Unit (S08CPUV2) 7.2.3 Stack Pointer (SP) This 16-bit address pointer register points at the next available location on the automatic last-in-first-out (LIFO) stack. The stack may be located anywhere in the 64-Kbyte address space that has RAM and can be any size up to the amount of available RAM. The stack is used to automatically save the return address for subroutine calls, the return address and CPU registers during interrupts, and for local variables.
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Chapter 7 Central Processor Unit (S08CPUV2) Table 7-1. CCR Register Field Descriptions Field Description 7 V Two’s Complement Overflow Flag — The CPU sets the overflow flag when a two’s complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag. 0 No overflow 1 Overflow 4 H Half-Carry Flag — The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (ADD) or add-with-carry (ADC) operation.
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Chapter 7 Central Processor Unit (S08CPUV2) of an operand for a test and then use relative addressing mode to specify the branch destination address when the tested condition is true. For BRCLR, BRSET, CBEQ, and DBNZ, the addressing mode listed in the instruction set tables is the addressing mode needed to access the operand to be tested, and relative addressing mode is implied for the branch destination. 7.3.
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Chapter 7 Central Processor Unit (S08CPUV2) 7.3.6.1 Indexed, No Offset (IX) This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of the operand needed to complete the instruction. 7.3.6.2 Indexed, No Offset with Post Increment (IX+) This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of the operand needed to complete the instruction.
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Chapter 7 Central Processor Unit (S08CPUV2) 7.4.1 Reset Sequence Reset can be caused by a power-on-reset (POR) event, internal conditions such as the COP (computer operating properly) watchdog, or by assertion of an external active-low reset pin. When a reset event occurs, the CPU immediately stops whatever it is doing (the MCU does not wait for an instruction boundary before responding to a reset event).
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Chapter 7 Central Processor Unit (S08CPUV2) 7.4.3 Wait Mode Operation The WAIT instruction enables interrupts by clearing the I bit in the CCR. It then halts the clocks to the CPU to reduce overall power consumption while the CPU is waiting for the interrupt or reset event that will wake the CPU from wait mode. When an interrupt or reset event occurs, the CPU clocks will resume and the interrupt or reset event will be processed normally.
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Chapter 7 Central Processor Unit (S08CPUV2) 7.5 HCS08 Instruction Set Summary Table 7-2 provides a summary of the HCS08 instruction set in all possible addressing modes. The table shows operand construction, execution time in internal bus clock cycles, and cycle-by-cycle details for each addressing mode variation of each instruction.
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Chapter 7 Central Processor Unit (S08CPUV2) Operation Object Code Cycles Source Form Address Mode Table 7-2. .
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Chapter 7 Central Processor Unit (S08CPUV2) Operation Object Code Cycles Source Form Address Mode Table 7-2. .
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Chapter 7 Central Processor Unit (S08CPUV2) CMP CMP CMP CMP CMP CMP CMP CMP #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP Operation Compare Accumulator with Memory A–M (CCR Updated But Operands Not Changed) Object Code IMM DIR EXT IX2 IX1 IX SP2 SP1 A1 B1 C1 D1 E1 F1 9E D1 9E E1 ii dd hh ll ee ff ff ee ff ff Cycles Source Form Address Mode Table 7-2. .
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Chapter 7 Central Processor Unit (S08CPUV2) INC opr8a INCA INCX INC oprx8,X INC ,X INC oprx8,SP Operation Increment M  (M) + $01 A  (A) + $01 X  (X) + $01 M  (M) + $01 M  (M) + $01 M  (M) + $01 Object Code Cycles Source Form Address Mode Table 7-2. .
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Chapter 7 Central Processor Unit (S08CPUV2) Operation Object Code Affect on CCR V11H INZC rpwpp rfwpp pwpp rfwpp 0 1 1 – – 42 5 ffffp – 1 1 0 – – – 0 DIR INH INH IX1 IX SP1 30 dd 40 50 60 ff 70 9E 60 ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp No Operation — Uses 1 Bus Cycle INH 9D 1 p – 1 1 – – – – – Nibble Swap Accumulator A  (A[3:0]:A[7:4]) INH 62 1 p – 1 1 – – – – – Inclusive OR Accumulator and Memory A  (A) | (M) IMM DIR EXT IX2 IX1 IX SP2 SP1 AA BA CA DA EA FA 9E DA 9E EA
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Chapter 7 Central Processor Unit (S08CPUV2) Operation Object Code Cycles Source Form Address Mode Table 7-2. .
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Chapter 7 Central Processor Unit (S08CPUV2) Operation Object Code V11H INZC 83 11 sssssvvfppp INH 84 1 p Transfer Accumulator to X (Index Register Low) X  (A) INH 97 1 p – 1 1 – – – – – Transfer CCR to Accumulator A  (CCR) INH 85 1 p – 1 1 – – – – – DIR INH INH IX1 IX SP1 3D dd 4D 5D 6D ff 7D 9E 6D ff 4 1 1 4 3 5 rfpp p p rfpp rfp prfpp 0 1 1 – – SWI Software Interrupt PC  (PC) + $0001 Push (PCL); SP  (SP) – $0001 Push (PCH); SP  (SP) – $0001 Push (X); SP  (SP) – $0001 Pus
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Chapter 7 Central Processor Unit (S08CPUV2) Operation Object Code Cycles Source Form Address Mode Table 7-2. . Instruction Set Summary (Sheet 9 of 9) Cyc-by-Cyc Details Affect on CCR V11H INZC TXS Transfer Index Reg. to SP SP  (H:X) – $0001 INH 94 2 fp – 1 1 – – – – – WAIT Enable Interrupts; Wait for Interrupt I bit  0; Halt CPU INH 8F 2+ fp...
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Chapter 7 Central Processor Unit (S08CPUV2) Table 7-3.
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Chapter 7 Central Processor Unit (S08CPUV2) Table 7-3.
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Chapter 7 Central Processor Unit (S08CPUV2) MC9S08AC16 Series Data Sheet, Rev.
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Chapter 8 Internal Clock Generator (S08ICGV4) The internal clock generation (ICG) module is used to generate the system clocks for the MC9S08AC16 Series MCU. The analog supply lines VDDA and VSSA are internally derived from the MCU’s VDD and VSS pins. Electrical parametric data for the ICG may be found in Appendix A, “Electrical Characteristics and Timing Specifications.
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10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC1) HCS08 CORE IRQ/TPMCLK CPU PTA7 PTA2 PTA1 PTA0 PTB3/AD1P3 PTB2/AD1P2 PTB1/TPM3CH1/AD1P1 PTB0/TPM3CH0/AD1P0 SDA1 IIC MODULE (IIC1) SCL1 INTERNAL CLOCK GENERATOR (ICG) EXTAL XTAL HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT PORT C RESET 4 AD1P11–AD1P8 DEBUG MODULE (DBG) BKGD/MS BDC 4 AD1P3–AD1P0 PORT A VDDAD VSSAD VREFL VREFH PORT B Chapter 8 Internal Clock Generator (S08ICGV4) PTC5/RxD2 PTC4 PTC3/TxD2 PTC2/MCLK PTC
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Internal Clock Generator (S08ICGV4) 8.1 Introduction The ICG provides multiple options for clock sources. This offers a user great flexibility when making choices between cost, precision, current draw, and performance. As seen in Figure 8-3, the ICG consists of four functional blocks. Each of these is briefly described here and then in more detail in a later section. • Oscillator block — The oscillator block provides means for connecting an external crystal or resonator.
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Internal Clock Generator (S08ICGV4) • • • • • • • 8.1.
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Internal Clock Generator (S08ICGV4) 8.1.3 Block Diagram Figure 8-3 is a top-level diagram that shows the functional organization of the internal clock generation (ICG) module. This section includes a general description and a feature list.
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Internal Clock Generator (S08ICGV4) 8.2.3 External Clock Connections If an external clock is used, then the pins are connected as shown Figure 8-4. ICG EXTAL XTAL VSS NOT CONNECTED CLOCK INPUT Figure 8-4. External Clock Connections 8.2.4 External Crystal/Resonator Connections If an external crystal/resonator frequency reference is used, then the pins are connected as shown in Figure 8-5. Recommended component values are listed in the Electrical Characteristics chapter.
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Internal Clock Generator (S08ICGV4) 8.3.1 R ICG Control Register 1 (ICGC1) 7 6 5 HGO1 RANGE REFS 0 1 0 4 3 2 1 OSCSTEN LOCD 1 0 0 0 CLKS W Reset 0 0 0 = Unimplemented or Reserved Figure 8-6. ICG Control Register 1 (ICGC1) 1 This bit can be written only once after reset. Additional writes are ignored. Table 8-1.
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Internal Clock Generator (S08ICGV4) 8.3.2 ICG Control Register 2 (ICGC2) 7 6 5 4 3 2 1 0 R LOLRE MFD LOCRE RFD W Reset 0 0 0 0 0 0 0 0 Figure 8-7. ICG Control Register 2 (ICGC2) Table 8-2. ICGC2 Register Field Descriptions Field Description 7 LOLRE Loss of Lock Reset Enable — The LOLRE bit determines what type of request is made by the ICG following a loss of lock indication. The LOLRE bit only has an effect when LOLS is set. 0 Generate an interrupt request on loss of lock.
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Internal Clock Generator (S08ICGV4) 8.3.3 ICG Status Register 1 (ICGS1) 7 R 6 CLKST 5 4 3 2 1 0 REFST LOLS LOCK LOCS ERCS ICGIF W Reset 1 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 8-8. ICG Status Register 1 (ICGS1) Table 8-3. ICGS1 Register Field Descriptions Field Description 7:6 CLKST Clock Mode Status — The CLKST bits indicate the current clock mode.
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Internal Clock Generator (S08ICGV4) 8.3.4 R ICG Status Register 2 (ICGS2) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 DCOS 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 8-9. ICG Status Register 2 (ICGS2) Table 8-4. ICGS2 Register Field Descriptions Field Description 0 DCOS DCO Clock Stable — The DCOS bit is set when the DCO clock (ICG2DCLK) is stable, meaning the count error has not changed by more than nunlock for two consecutive samples and the DCO clock is not static.
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Internal Clock Generator (S08ICGV4) 7 6 5 4 3 2 1 0 0 0 0 0 R FLT W Reset 1 1 0 0 Figure 8-11. ICG Lower Filter Register (ICGFLTL) Table 8-6. ICGFLTL Register Field Descriptions Field Description 7:0 FLT Filter Value — The FLT bits indicate the current filter value, which controls the DCO frequency. The FLT bits are read only except when the CLKS bits are programmed to self-clocked mode (CLKS = 00). In self-clocked mode, any write to ICGFLTU updates the current 12-bit filter value.
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Internal Clock Generator (S08ICGV4) 8.4.1 Off Mode (Off) Normally when the CPU enters stop mode, the ICG will cease all clock activity and is in the off state. However there are two cases to consider when clock activity continues while the CPU is in stop mode, 8.4.1.1 BDM Active When the BDM is enabled, the ICG continues activity as originally programmed. This allows access to memory and control registers via the BDC controller. 8.4.1.
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Internal Clock Generator (S08ICGV4) entering off mode. If CLKS bits are set to 01 or 11 coming out of the Off state, the ICG enters this mode until ICGDCLK is stable as determined by the DCOS bit. After ICGDCLK is considered stable, the ICG automatically closes the loop by switching to FLL engaged (internal or external) as selected by the CLKS bits.
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Internal Clock Generator (S08ICGV4) 8.4.4 FLL Engaged Internal Unlocked FEI unlocked is a temporary state that is entered when FEI is entered and the count error (n) output from the subtractor is greater than the maximum nunlock or less than the minimum nunlock, as required by the lock detector to detect the unlock condition.
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Internal Clock Generator (S08ICGV4) 8.4.7.1 FLL Engaged External Unlocked FEE unlocked is entered when FEE is entered and the count error (n) output from the subtractor is greater than the maximum nunlock or less than the minimum nunlock, as required by the lock detector to detect the unlock condition. The ICG will remain in this state while the count error (n) is greater than the maximum nlock or less than the minimum nlock, as required by the lock detector to detect the lock condition.
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Internal Clock Generator (S08ICGV4) 8.4.9 FLL Loss-of-Clock Detection The reference clock and the DCO clock are monitored under different conditions (see Table 8-8). Provided the reference frequency is being monitored, ERCS = 1 indicates that the reference clock meets minimum frequency requirements. When the reference and/or DCO clock(s) are being monitored, if either one falls below a certain frequency, fLOR and fLOD, respectively, the LOCS status bit will be set to indicate the error.
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Internal Clock Generator (S08ICGV4) 8.4.10 Clock Mode Requirements A clock mode is requested by writing to CLKS1:CLKS0 and the actual clock mode is indicated by CLKST1:CLKST0. Provided minimum conditions are met, the status shown in CLKST1:CLKST0 should be the same as the requested mode in CLKS1:CLKS0. Table 8-9 shows the relationship between CLKS, CLKST, and ICGOUT. It also shows the conditions for CLKS = CLKST or the reason CLKS  CLKST.
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Internal Clock Generator (S08ICGV4) 8.4.11 Fixed Frequency Clock The ICG provides a fixed frequency clock output, XCLK, for use by on-chip peripherals. This output is equal to the internal bus clock, BUSCLK, in all modes except FEE. In FEE mode, XCLK is equal to ICGERCLK 2 when the following conditions are met: • (P N) R  4 where P is determined by RANGE (see Table 8-11), N and R are determined by MFD and RFD respectively (see Table 8-12). • LOCK = 1.
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Internal Clock Generator (S08ICGV4) Table 8-10. ICG Configuration Consideration Clock Reference Source = Internal 1 Clock Reference Source = External FLL Engaged FEI 4 MHz < fBus < 20 MHz. Medium power (will be less than FEE if oscillator range = high) Good clock accuracy (After IRG is trimmed) Lowest system cost (no external components required) IRG is on. DCO is on.
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Internal Clock Generator (S08ICGV4) Table 8-12. MFD and RFD Decode Table 101 110 111 8.5.2 14 16 18 101 110 111 32 64 128 Example #1: External Crystal = 32 kHz, Bus Frequency = 4.19 MHz In this example, the FLL will be used (in FEE mode) to multiply the external 32 kHz oscillator up to 8.38 MHz to achieve 4.19 MHz bus frequency. After the MCU is released from reset, the ICG is in self-clocked mode (SCM) and supplies approximately 8 MHz on ICGOUT, which corresponds to a 4 MHz bus frequency (fBus).
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Internal Clock Generator (S08ICGV4) Bits 11:0 FLT No need for user initialization ICGTRM = $xx Bits 7:0 TRIM Only need to write when trimming internal oscillator; not used when external crystal is clock source Figure 8-14 shows flow charts for three conditions requiring ICG initialization. RESET INITIALIZE ICG ICGC1 = $38 ICGC2 = $00 CHECK FLL LOCK STATUS.
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Internal Clock Generator (S08ICGV4) 8.5.3 Example #2: External Crystal = 4 MHz, Bus Frequency = 20 MHz In this example, the FLL will be used (in FEE mode) to multiply the external 4 MHz oscillator up to 40-MHz to achieve 20 MHz bus frequency. After the MCU is released from reset, the ICG is in self-clocked mode (SCM) and supplies approximately 8 MHz on ICGOUT which corresponds to a 4 MHz bus frequency (fBus).
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Internal Clock Generator (S08ICGV4) RECOVERY FROM STOP RESET INITIALIZE ICG ICGC1 = $7A ICGC2 = $30 CHECK FLL LOCK STATUS LOCK = 1? YES SERVICE INTERRUPT SOURCE (fBus = 4 MHz) NO CHECK FLL LOCK STATUS LOCK = 1? NO YES CONTINUE CONTINUE Figure 8-15. ICG Initialization and Stop Recovery for Example #2 MC9S08AC16 Series Data Sheet, Rev.
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Internal Clock Generator (S08ICGV4) 8.5.4 Example #3: No External Crystal Connection, 5.4 MHz Bus Frequency In this example, the FLL will be used (in FEI mode) to multiply the internal 243 kHz (approximate) reference clock up to 10.8 MHz to achieve 5.4 MHz bus frequency. This system will also use the trim function to fine tune the frequency based on an external reference signal.
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Internal Clock Generator (S08ICGV4) ICGTRM = $xx Bit 7:0 TRIM Only need to write when trimming internal oscillator; done in separate operation (see example #4) RECOVERY FROM STOP RESET INITIALIZE ICG ICGC1 = $28 ICGC2 = $31 CHECK FLL LOCK STATUS. LOCK = 1? CHECK FLL LOCK STATUS. LOCK = 1? NO YES NO CONTINUE YES CONTINUE NOTE: THIS WILL REQUIRE THE INTERAL REFERENCE CLOCK TO START AND STABILIZE. Figure 8-16. ICG Initialization and Stop Recovery for Example #3 MC9S08AC16 Series Data Sheet, Rev.
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Internal Clock Generator (S08ICGV4) 8.5.5 Example #4: Internal Clock Generator Trim The internally generated clock source is guaranteed to have a period  25% of the nominal value. In some cases, this may be sufficient accuracy. For other applications that require a tight frequency tolerance, a trimming procedure is provided that will allow a very accurate source. This section outlines one example of trimming the internal oscillator. Many other possible trimming procedures are valid and can be used.
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Chapter 9 Keyboard Interrupt (S08KBIV1) 9.1 Introduction The MC9S08AC16 Series has one KBI module with seven keyboard interrupt inputs that are shared with port D and port G pins. See Chapter 2, “Pins and Connections,” for more information about the logic and hardware aspects of these pins. NOTE Bit 7 of KBISC and KBIPE is reserved and reads 0. Neglect the correlative information in Section 9.4.1, “KBI Status and Control Register (KBISC),” and Section 9.4.2, “KBI Pin Enable Register (KBIPE).” 9.
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10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC1) HCS08 CORE IRQ/TPMCLK CPU PTA7 PTA2 PTA1 PTA0 PTB3/AD1P3 PTB2/AD1P2 PTB1/TPM3CH1/AD1P1 PTB0/TPM3CH0/AD1P0 SDA1 IIC MODULE (IIC1) SCL1 INTERNAL CLOCK GENERATOR (ICG) EXTAL XTAL HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT PORT C RESET 4 AD1P11–AD1P8 DEBUG MODULE (DBG) BKGD/MS BDC 4 AD1P3–AD1P0 PORT A VDDAD VSSAD VREFL VREFH PORT B Chapter 9 Keyboard Interrupt (S08KBIV1) PTC5/RxD2 PTC4 PTC3/TxD2 PTC2/MCLK PTC1/SDA1
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Keyboard Interrupt (S08KBIV1) 9.3.1 KBI Block Diagram Figure 9-2 shows the block diagram for a KBI module. KBIP0 KBIPE0 VDD KBIPE3 0 S SYNCHRONIZER KBIPE4 KEYBOARD INTERRUPT FF STOP STOP BYPASS KEYBOARD INTERRUPT REQUEST KBIMOD 1 0 KBF CK KBEDG4 KBIPn RESET D CLR Q 1 KBIP4 BUSCLK KBACK KBIP3 S KBIE KBIPEn KBEDGn Figure 9-2. KBI Block Diagram 9.4 Register Definition This section provides information about all registers and control bits associated with the KBI module.
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Keyboard Interrupt (S08KBIV1) 9.4.1 KBI Status and Control Register (KBISC) 7 6 5 4 KBEDG7 KBEDG6 KBEDG5 KBEDG4 R 3 2 KBF 0 W Reset 1 0 KBIE KBIMOD 0 0 KBACK 0 0 0 0 0 0 = Unimplemented or Reserved Figure 9-3. KBI Status and Control Register (KBISC) Table 9-1.
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Keyboard Interrupt (S08KBIV1) 9.4.2 KBI Pin Enable Register (KBIPE) 7 6 5 4 3 2 1 0 KBIPE7 KBIPE6 KBIPE5 KBIPE4 KBIPE3 KBIPE2 KBIPE1 KBIPE0 0 0 0 0 0 0 0 0 R W Reset = Unimplemented or Reserved Figure 9-4. KBI Pin Enable Register (KBIPE) Table 9-2. KBIPE Register Field Descriptions Field Description 7:0 KBIPE[7:0] 9.5 9.5.
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Keyboard Interrupt (S08KBIV1) 9.5.3 KBI Interrupt Controls The KBF status flag becomes set (1) when an edge event has been detected on any KBI input pin. If KBIE = 1 in the KBISC register, a hardware interrupt will be requested whenever KBF = 1. The KBF flag is cleared by writing a 1 to the keyboard acknowledge (KBACK) bit. When KBIMOD = 0 (selecting edge-only operation), KBF is always cleared by writing 1 to KBACK.
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Chapter 10 Timer/PWM (S08TPMV3) 10.1 Introduction The MC9S08AC16 Series includes three independent timer/PWM (TPM) modules which support traditional input capture, output compare, or buffered edge-aligned pulse-width modulation (PWM) on each channel. A control bit in each TPM configures all channels in that timer to operate as center-aligned PWM functions.
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10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC1) HCS08 CORE IRQ/TPMCLK CPU PTA7 PTA2 PTA1 PTA0 PTB3/AD1P3 PTB2/AD1P2 PTB1/TPM3CH1/AD1P1 PTB0/TPM3CH0/AD1P0 SDA1 IIC MODULE (IIC1) SCL1 INTERNAL CLOCK GENERATOR (ICG) EXTAL XTAL HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT PORT C RESET 4 AD1P11–AD1P8 DEBUG MODULE (DBG) BKGD/MS BDC 4 AD1P3–AD1P0 PORT A VDDAD VSSAD VREFL VREFH PORT B Chapter 10 Timer/PWM (S08TPMV3) PTC5/RxD2 PTC4 PTC3/TxD2 PTC2/MCLK PTC1/SDA1 PTC0/SC
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Chapter 10 Timer/PWM (S08TPMV3) 10.3 TPMV3 Differences from Previous Versions The TPMV3 is the latest version of the Timer/PWM module that addresses errata found in previous versions. The following section outlines the differences between TPMV3 and TPMV2 modules, and any considerations that should be taken when porting code. Table 10-1.
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Chapter 10 Timer/PWM (S08TPMV3) Table 10-1. TPMV2 and TPMV3 Porting Considerations (continued) Action TPMV3 TPMV2 In Edge-Aligned PWM mode when (CLKSB:CLKSA not = 00), Update the TPMxCnVH:L writes to TPMxCnVH:L registers registers with the value of their write buffer after both bytes were written and when the TPM counter changes from (TPMxMODH:L - 1) to (TPMxMODH:L). Note: If the TPM counter is a free-running counter, then this update is made when the TPM counter changes from $FFFE to $FFFF.
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Chapter 10 Timer/PWM (S08TPMV3) 8 For more information, refer to Section 10.6.2.4, “Center-Aligned PWM Mode.” [SE110-TPM case 4] 10.3.1 Migrating from TPMV1 In addition to Section 10.3, “TPMV3 Differences from Previous Versions,” keep in mind the following considerations when migrating from a device that uses TPMV1. • You can write to the Channel Value register (TPMxCnV) when the timer is not in input capture mode for TPMV2, not TPMV3.
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Timer/PWM Module (S08TPMV3) 10.3.
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Timer/PWM Module (S08TPMV3) • • Edge-aligned PWM mode The value of a 16-bit modulo register plus 1 sets the period of the PWM output signal. The channel value register sets the duty cycle of the PWM output signal. The user may also choose the polarity of the PWM output signal. Interrupts are available at the end of the period and at the duty-cycle transition point.
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Timer/PWM Module (S08TPMV3) BUS CLOCK FIXED SYSTEM CLOCK SYNC EXTERNAL CLOCK CLOCK SOURCE SELECT OFF, BUS, FIXED SYSTEM CLOCK, EXT PRESCALE AND SELECT ³1, 2, 4, 8, 16, 32, 64, or ³128 CLKSB:CLKSA PS2:PS1:PS0 CPWMS 16-BIT COUNTER TOF COUNTER RESET TOIE INTERRUPT LOGIC 16-BIT COMPARATOR TPMxMODH:TPMxMODL CHANNEL 0 ELS0B ELS0A PORT LOGIC TPMxCH0 16-BIT COMPARATOR TPMxC0VH:TPMxC0VL CH0F INTERNAL BUS 16-BIT LATCH CHANNEL 1 MS0B MS0A ELS1B ELS1A CH0IE INTERRUPT LOGIC PORT LOGIC TPMx
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Timer/PWM Module (S08TPMV3) The TPM channels are programmable independently as input capture, output compare, or edge-aligned PWM channels. Alternately, the TPM can be configured to produce CPWM outputs on all channels. When the TPM is configured for CPWMs, the counter operates as an up/down counter; input capture, output compare, and EPWM functions are not practical. If a channel is configured as input capture, an internal pullup device may be enabled for that channel.
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Timer/PWM Module (S08TPMV3) 10.4.1.1 EXTCLK — External Clock Source Control bits in the timer status and control register allow the user to select nothing (timer disable), the bus-rate clock (the normal default source), a crystal-related clock, or an external clock as the clock which drives the TPM prescaler and subsequently the 16-bit TPM counter. The external clock source is synchronized in the TPM.
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Timer/PWM Module (S08TPMV3) When a channel is configured for edge-aligned PWM (CPWMS=0, MSnB=1 and ELSnB:ELSnA not = 0:0), the data direction is overridden, the TPMxCHn pin is forced to be an output controlled by the TPM, and ELSnA controls the polarity of the PWM output signal on the pin. When ELSnB:ELSnA=1:0, the TPMxCHn pin is forced high at the start of each new period (TPMxCNT=0x0000), and the pin is forced low when the channel value register matches the timer counter.
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Timer/PWM Module (S08TPMV3) When the TPM is configured for center-aligned PWM (and ELSnB:ELSnA not = 0:0), the data direction for all channels in this TPM are overridden, the TPMxCHn pins are forced to be outputs controlled by the TPM, and the ELSnA bits control the polarity of each TPMxCHn output.
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Timer/PWM Module (S08TPMV3) 10.5 Register Definition This section consists of register descriptions in address order. A typical MCU system may contain multiple TPMs, and each TPM may have one to eight channels, so register names include placeholder characters to identify which TPM and which channel is being referenced. For example, TPMxCnSC refers to timer (TPM) x, channel n. TPM1C2SC would be the status and control register for channel 2 of timer 1. 10.5.
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Timer/PWM Module (S08TPMV3) Table 10-4. TPMxSC Field Descriptions (continued) Field Description 4–3 Clock source selects. As shown in Table 10-5, this 2-bit field is used to disable the TPM system or select one of CLKS[B:A] three clock sources to drive the counter prescaler. The fixed system clock source is only meaningful in systems with a PLL-based or FLL-based system clock. When there is no PLL or FLL, the fixed-system clock source is the same as the bus rate clock.
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Timer/PWM Module (S08TPMV3) Reset clears the TPM counter registers. Writing any value to TPMxCNTH or TPMxCNTL also clears the TPM counter (TPMxCNTH:TPMxCNTL) and resets the coherency mechanism, regardless of the data involved in the write. R 7 6 5 4 3 2 1 0 Bit 15 14 13 12 11 10 9 Bit 8 0 0 W Reset Any write to TPMxCNTH clears the 16-bit counter 0 0 0 0 0 0 Figure 10-8.
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Timer/PWM Module (S08TPMV3) When BDM is active, the coherency mechanism is frozen (unless reset by writing to TPMxSC register) such that the buffer latches remain in the state they were in when the BDM became active, even if one or both halves of the modulo register are written while BDM is active. Any write to the modulo registers bypasses the buffer latches and directly writes to the modulo register while BDM is active.
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Timer/PWM Module (S08TPMV3) Table 10-7. TPMxCnSC Field Descriptions Field Description 7 CHnF Channel n flag. When channel n is an input-capture channel, this read/write bit is set when an active edge occurs on the channel n pin. When channel n is an output compare or edge-aligned/center-aligned PWM channel, CHnF is set when the value in the TPM counter registers matches the value in the TPM channel n value registers.
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Timer/PWM Module (S08TPMV3) Table 10-8.
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Timer/PWM Module (S08TPMV3) (becomes unlatched) when the TPMxCnSC register is written (whether BDM mode is active or not). Any write to the channel registers will be ignored during the input capture mode. When BDM is active, the coherency mechanism is frozen (unless reset by writing to TPMxCnSC register) such that the buffer latches remain in the state they were in when the BDM became active, even if one or both halves of the channel register are read while BDM is active.
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Timer/PWM Module (S08TPMV3) The following sections describe the main counter and each of the timer operating modes (input capture, output compare, edge-aligned PWM, and center-aligned PWM). Because details of pin operation and interrupt activity depend upon the operating mode, these topics will be covered in the associated mode explanation sections. 10.6.1 Counter All timer functions are based on the main 16-bit counter (TPMxCNTH:TPMxCNTL).
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Timer/PWM Module (S08TPMV3) to avoid such settings.) The TPM channel could still be used in output compare mode for software timing functions (pin controls set not to affect the TPM channel pin). 10.6.1.2 Counter Overflow and Modulo Reset An interrupt flag and enable are associated with the 16-bit main counter. The flag (TOF) is a software-accessible indication that the timer counter has overflowed.
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Timer/PWM Module (S08TPMV3) 10.6.2.1 Input Capture Mode With the input-capture function, the TPM can capture the time at which an external event occurs. When an active edge occurs on the pin of an input-capture channel, the TPM latches the contents of the TPM counter into the channel-value registers (TPMxCnVH:TPMxCnVL). Rising edges, falling edges, or any edge may be chosen as the active edge that triggers an input capture. In input capture mode, the TPMxCnVH and TPMxCnVL registers are read only.
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Timer/PWM Module (S08TPMV3) OVERFLOW OVERFLOW OVERFLOW PERIOD PULSE WIDTH TPMxCHn OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE Figure 10-15. PWM Period and Pulse Width (ELSnA=0) When the channel value register is set to 0x0000, the duty cycle is 0%. 100% duty cycle can be achieved by setting the timer-channel register (TPMxCnVH:TPMxCnVL) to a value greater than the modulus setting. This implies that the modulus setting must be less than 0xFFFF in order to get 100% duty cycle.
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Timer/PWM Module (S08TPMV3) The output compare value in the TPM channel registers (times 2) determines the pulse width (duty cycle) of the CPWM signal (Figure 10-16). If ELSnA=0, a compare occurred while counting up forces the CPWM output signal low and a compare occurred while counting down forces the output high. The counter counts up until it reaches the modulo setting in TPMxMODH:TPMxMODL, then counts down until it reaches zero. This sets the period equal to two times TPMxMODH:TPMxMODL.
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Timer/PWM Module (S08TPMV3) 10.7 10.7.1 Reset Overview General The TPM is reset whenever any MCU reset occurs. 10.7.2 Description of Reset Operation Reset clears the TPMxSC register which disables clocks to the TPM and disables timer overflow interrupts (TOIE=0).
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Timer/PWM Module (S08TPMV3) to enable hardware interrupt generation. While the interrupt enable bit is set, a static interrupt will generate whenever the associated interrupt flag equals one. The user’s software must perform a sequence of steps to clear the interrupt flag before returning from the interrupt-service routine. TPM interrupt flags are cleared by a two-step process including a read of the flag bit while it is set (1) followed by a write of zero (0) to the bit.
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Timer/PWM Module (S08TPMV3) 10.8.2.2.3 PWM End-of-Duty-Cycle Events For channels configured for PWM operation there are two possibilities. When the channel is configured for edge-aligned PWM, the channel flag gets set when the timer counter matches the channel value register which marks the end of the active duty cycle period. When the channel is configured for center-aligned PWM, the timer count matches the channel value register twice during each PWM cycle.
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Timer/PWM Module (S08TPMV3) prescaler counting) after the second byte is written. Instead, the TPM v2 always updates these registers when their second byte is written. The following procedure can be used in the TPM v3 to verify if the TPMxCnVH:L registers were updated with the new value that was written to these registers (value in their write buffer). ...
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Timer/PWM Module (S08TPMV3) — TPMxCnVH:L is changed from a non-zero value to 0x0000 [SE110-TPM case 4] In this case, the TPM v3 finishes the current PWM period using the old duty cycle setting. Instead, the TPM v2 finishes the current PWM period using the new duty cycle setting. 6. Write to TPMxMODH:L registers in BDM mode (Section 10.5.3, “TPM Counter Modulo Registers (TPMxMODH:TPMxMODL)) In the TPM v3 a write to TPMxSC register in BDM mode clears the write coherency mechanism of TPMxMODH:L registers.
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Timer/PWM Module (S08TPMV3) EPWM mode TPMxMODH:TPMxMODL = 0x0007 TPMxCnVH:TPMxCnVL = 0x0005 RESET (active low) BUS CLOCK TPMxCNTH:TPMxCNTL 0 1 00 CLKSB:CLKSA BITS 2 3 4 5 6 7 0 1 2 ... 01 MSnB:MSnA BITS 00 10 ELSnB:ELSnA BITS 00 01 TPMv2 TPMxCHn TPMv3 TPMxCHn CHnF BIT (in TPMv2 and TPMv3) Figure 10-18.
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Chapter 11 Serial Communications Interface (S08SCIV4) 11.1 Introduction The MC9S08AC16 Series includes two independent serial communications interface (SCI) modules which are sometimes called universal asynchronous receiver/transmitters (UARTs). Typically, these systems are used to connect to the RS232 serial input/output (I/O) port of a personal computer or workstation, but they can also be used to communicate with other embedded controllers.
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10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC1) HCS08 CORE IRQ/TPMCLK CPU PTA7 PTA2 PTA1 PTA0 PTB3/AD1P3 PTB2/AD1P2 PTB1/TPM3CH1/AD1P1 PTB0/TPM3CH0/AD1P0 SDA1 IIC MODULE (IIC1) SCL1 INTERNAL CLOCK GENERATOR (ICG) EXTAL XTAL HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT PORT C RESET 4 AD1P11–AD1P8 DEBUG MODULE (DBG) BKGD/MS BDC 4 AD1P3–AD1P0 PORT A VDDAD VSSAD VREFL VREFH PORT B Chapter 11 Serial Communications Interface (S08SCIV4) PTC5/RxD2 PTC4 PTC3/TxD2 PTC2/
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Serial Communications Interface (S08SCIV4) 11.1.
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Serial Communications Interface (S08SCIV4) 11.1.3 Block Diagram Figure 11-2 shows the transmitter portion of the SCI.
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Serial Communications Interface (S08SCIV4) Figure 11-3 shows the receiver portion of the SCI.
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Serial Communications Interface (S08SCIV4) 11.2 Register Definition The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for transmit/receive data. Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all SCI registers. This section refers to registers and control bits only by their names. 11.2.
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Serial Communications Interface (S08SCIV4) Table 11-2. SCIxBDL Field Descriptions Field 7:0 SBR[7:0] 11.2.2 Description Baud Rate Modulo Divisor — These 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo divide rate for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to reduce supply current. When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16BR). See also BR bits in Table 11-1.
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Serial Communications Interface (S08SCIV4) Table 11-3. SCIxC1 Field Descriptions (continued) Field Description 1 PE Parity Enable — Enables hardware parity generation and checking. When parity is enabled, the most significant bit (MSB) of the data character (eighth or ninth data bit) is treated as the parity bit. 0 No hardware parity generation or checking. 1 Parity enabled. 0 PT Parity Type — Provided parity is enabled (PE = 1), this bit selects even or odd parity.
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Serial Communications Interface (S08SCIV4) Table 11-4. SCIxC2 Field Descriptions (continued) Field Description 2 RE Receiver Enable — When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin. If LOOPS = 1 the RxD pin reverts to being a general-purpose I/O pin even if RE = 1. 0 Receiver off. 1 Receiver on.
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Serial Communications Interface (S08SCIV4) Table 11-5. SCIxS1 Field Descriptions Field Description 7 TDRE Transmit Data Register Empty Flag — TDRE is set out of reset and when a transmit data value transfers from the transmit data buffer to the transmit shifter, leaving room for a new character in the buffer. To clear TDRE, read SCIxS1 with TDRE = 1 and then write to the SCI data register (SCIxD). 0 Transmit data register (buffer) full. 1 Transmit data register (buffer) empty.
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Serial Communications Interface (S08SCIV4) Table 11-5. SCIxS1 Field Descriptions (continued) Field Description 1 FE Framing Error Flag — FE is set at the same time as RDRF when the receiver detects a logic 0 where the stop bit was expected. This suggests the receiver was not properly aligned to a character frame. To clear FE, read SCIxS1 with FE = 1 and then read the SCI data register (SCIxD). 0 No framing error detected. This does not guarantee the framing is correct. 1 Framing error.
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Serial Communications Interface (S08SCIV4) Table 11-6. SCIxS2 Field Descriptions (continued) 1 Field Description 1 LBKDE LIN Break Detection Enable— LBKDE is used to select a longer break character detection length. While LBKDE is set, framing error (FE) and receive data register full (RDRF) flags are prevented from setting. 0 Break character is detected at length of 10 bit times (11 if M = 1). 1 Break character is detected at length of 11 bit times (12 if M = 1).
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Serial Communications Interface (S08SCIV4) Table 11-7. SCIxC3 Field Descriptions (continued) Field 4 TXINV1 1 Description Transmit Data Inversion — Setting this bit reverses the polarity of the transmitted data output. 0 Transmit data not inverted 1 Transmit data inverted 3 ORIE Overrun Interrupt Enable — This bit enables the overrun flag (OR) to generate hardware interrupt requests. 0 OR interrupts disabled (use polling). 1 Hardware interrupt requested when OR = 1.
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Serial Communications Interface (S08SCIV4) MODULO DIVIDE BY (1 THROUGH 8191) BUSCLK SBR12:SBR0 BAUD RATE GENERATOR OFF IF [SBR12:SBR0] = 0 DIVIDE BY 16 Tx BAUD RATE Rx SAMPLING CLOCK (16  BAUD RATE) BAUD RATE = BUSCLK [SBR12:SBR0]  16 Figure 11-12. SCI Baud Rate Generation SCI communications require the transmitter and receiver (which typically derive baud rates from independent clock sources) to use the same baud rate.
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Serial Communications Interface (S08SCIV4) Writing 0 to TE does not immediately release the pin to be a general-purpose I/O pin. Any transmit activity that is in progress must first be completed. This includes data characters in progress, queued idle characters, and queued break characters. 11.3.2.1 Send Break and Queued Idle The SBK control bit in SCIxC2 is used to send break characters which were originally used to gain the attention of old teletype receivers.
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Serial Communications Interface (S08SCIV4) status flag is set. If RDRF was already set indicating the receive data register (buffer) was already full, the overrun (OR) status flag is set and the new data is lost. Because the SCI receiver is double-buffered, the program has one full character time after RDRF is set before the data in the receive data buffer must be read to avoid a receiver overrun.
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Serial Communications Interface (S08SCIV4) message characters. At the end of a message, or at the beginning of the next message, all receivers automatically force RWU to 0 so all receivers wake up in time to look at the first character(s) of the next message. 11.3.3.2.1 Idle-Line Wakeup When WAKE = 0, the receiver is configured for idle-line wakeup. In this mode, RWU is cleared automatically when the receiver detects a full character time of the idle-line level.
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Serial Communications Interface (S08SCIV4) Instead of hardware interrupts, software polling may be used to monitor the TDRE and TC status flags if the corresponding TIE or TCIE local interrupt masks are 0s. When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive data register by reading SCIxD. The RDRF flag is cleared by reading SCIxS1 while RDRF = 1 and then reading SCIxD.
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Serial Communications Interface (S08SCIV4) 11.3.5.2 Stop Mode Operation During all stop modes, clocks to the SCI module are halted. In stop1 and stop2 modes, all SCI register data is lost and must be re-initialized upon recovery from these two stop modes. No SCI module registers are affected in stop3 mode. The receive input active edge detect circuit is still active in stop3 mode, but not in stop2..
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Serial Communications Interface (S08SCIV4) MC9S08AC16 Series Data Sheet, Rev.
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Chapter 12 Serial Peripheral Interface (S08SPIV3) 12.1 Introduction The MC9S08AC16 Series has one serial peripheral interface (SPI) module. The four pins associated with SPI functionality are shared with port E pins 4–7. See Appendix A, “Electrical Characteristics and Timing Specifications,” for SPI electrical parametric information. NOTE Ignore any references to stop1 low-power mode in this chapter, because the MC9S08AC16 Series does not support it. MC9S08AC16 Series Data Sheet, Rev.
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10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC1) HCS08 CORE IRQ/TPMCLK CPU PTA7 PTA2 PTA1 PTA0 PTB3/AD1P3 PTB2/AD1P2 PTB1/TPM3CH1/AD1P1 PTB0/TPM3CH0/AD1P0 SDA1 IIC MODULE (IIC1) SCL1 INTERNAL CLOCK GENERATOR (ICG) EXTAL XTAL HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT PORT C RESET 4 AD1P11–AD1P8 DEBUG MODULE (DBG) BKGD/MS BDC 4 AD1P3–AD1P0 PORT A VDDAD VSSAD VREFL VREFH PORT B Chapter 12 Serial Peripheral Interface (S08SPIV3) PTC5/RxD2 PTC4 PTC3/TxD2 PTC2/MCLK
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Serial Peripheral Interface (S08SPIV3) 12.1.1 Features Features of the SPI module include: • Master or slave mode operation • Full-duplex or single-wire bidirectional option • Programmable transmit bit rate • Double-buffered transmit and receive • Serial clock phase and polarity options • Slave select output • Selectable MSB-first or LSB-first shifting 12.1.
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Serial Peripheral Interface (S08SPIV3) The most common uses of the SPI system include connecting simple shift registers for adding input or output ports or connecting small peripheral devices such as serial A/D or D/A converters. Although Figure 12-2 shows a system where data is exchanged between two MCUs, many practical systems involve simpler connections where data is unidirectionally transferred from the master MCU to a slave or from a slave to the master MCU. 12.1.2.
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Serial Peripheral Interface (S08SPIV3) PIN CONTROL M SPE MOSI (MOMI) S Tx BUFFER (WRITE SPI1D) ENABLE SPI SYSTEM M SHIFT OUT SPI SHIFT REGISTER SHIFT IN MISO (SISO) S SPC0 Rx BUFFER (READ SPI1D) BIDIROE SHIFT DIRECTION LSBFE SHIFT CLOCK Rx BUFFER FULL Tx BUFFER EMPTY MASTER CLOCK BUS RATE CLOCK SPIBR CLOCK GENERATOR MSTR CLOCK LOGIC SLAVE CLOCK MASTER/SLAVE M SPSCK S MASTER/ SLAVE MODE SELECT MODFEN SSOE MODE FAULT DETECTION SPRF SS SPTEF SPTIE MODF SPIE SPI INTERRUPT REQUEST
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Serial Peripheral Interface (S08SPIV3) BUS CLOCK PRESCALER CLOCK RATE DIVIDER DIVIDE BY 1, 2, 3, 4, 5, 6, 7, or 8 DIVIDE BY 2, 4, 8, 16, 32, 64, 128, or 256 SPPR2:SPPR1:SPPR0 SPR2:SPR1:SPR0 MASTER SPI BIT RATE Figure 12-4. SPI Baud Rate Generation 12.2 External Signal Description The SPI optionally shares four port pins. The function of these pins depends on the settings of SPI control bits.
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Serial Peripheral Interface (S08SPIV3) 12.3 Modes of Operation 12.3.1 SPI in Stop Modes The SPI is disabled in all stop modes, regardless of the settings before executing the STOP instruction. During either stop1 or stop2 mode, the SPI module will be fully powered down. Upon wake-up from stop1 or stop2 mode, the SPI module will be in the reset state. During stop3 mode, clocks to the SPI module are halted. No registers are affected.
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Serial Peripheral Interface (S08SPIV3) Table 12-1. SPI1C1 Field Descriptions (continued) Field Description 4 MSTR Master/Slave Mode Select 0 SPI module configured as a slave SPI device 1 SPI module configured as a master SPI device 3 CPOL Clock Polarity — This bit effectively places an inverter in series with the clock signal from a master SPI or to a slave SPI device. Refer to Section 12.5.1, “SPI Clock Formats” for more details.
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Serial Peripheral Interface (S08SPIV3) Table 12-3. SPI1C2 Register Field Descriptions Field Description 4 MODFEN Master Mode-Fault Function Enable — When the SPI is configured for slave mode, this bit has no meaning or effect. (The SS pin is the slave select input.) In master mode, this bit determines how the SS pin is used (refer to Table 12-2 for more details).
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Serial Peripheral Interface (S08SPIV3) Table 12-5. SPI Baud Rate Prescaler Divisor SPPR2:SPPR1:SPPR0 Prescaler Divisor 0:0:0 1 0:0:1 2 0:1:0 3 0:1:1 4 1:0:0 5 1:0:1 6 1:1:0 7 1:1:1 8 Table 12-6. SPI Baud Rate Divisor 12.4.4 SPR2:SPR1:SPR0 Rate Divisor 0:0:0 2 0:0:1 4 0:1:0 8 0:1:1 16 1:0:0 32 1:0:1 64 1:1:0 128 1:1:1 256 SPI Status Register (SPI1S) This register has three read-only status bits. Bits 6, 3, 2, 1, and 0 are not implemented and always read 0.
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Serial Peripheral Interface (S08SPIV3) Table 12-7. SPI1S Register Field Descriptions Field Description 7 SPRF SPI Read Buffer Full Flag — SPRF is set at the completion of an SPI transfer to indicate that received data may be read from the SPI data register (SPI1D). SPRF is cleared by reading SPRF while it is set, then reading the SPI data register.
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Serial Peripheral Interface (S08SPIV3) 12.5 Functional Description An SPI transfer is initiated by checking for the SPI transmit buffer empty flag (SPTEF = 1) and then writing a byte of data to the SPI data register (SPI1D) in the master SPI device. When the SPI shift register is available, this byte of data is moved from the transmit data buffer to the shifter, SPTEF is set to indicate there is room in the buffer to queue another transmit character if desired, and the SPI serial transfer starts.
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Serial Peripheral Interface (S08SPIV3) MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1). The master SS output goes to active low one-half SPSCK cycle before the start of the transfer and goes back high at the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a slave. BIT TIME # (REFERENCE) 1 2 ...
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Serial Peripheral Interface (S08SPIV3) in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1).
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Serial Peripheral Interface (S08SPIV3) 12.5.2 SPI Interrupts There are three flag bits, two interrupt mask bits, and one interrupt vector associated with the SPI system. The SPI interrupt enable mask (SPIE) enables interrupts from the SPI receiver full flag (SPRF) and mode fault flag (MODF). The SPI transmit interrupt enable mask (SPTIE) enables interrupts from the SPI transmit buffer empty flag (SPTEF).
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Serial Peripheral Interface (S08SPIV3) MC9S08AC16 Series Data Sheet, Rev.
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Chapter 13 Inter-Integrated Circuit (S08IICV2) 13.1 Introduction The MC9S08AC16 Series series of microcontrollers has an inter-integrated circuit (IIC) module for communication with other integrated circuits. The two pins associated with this module, SCL and SDA, are shared with port C pins 0 and 1, respectively. NOTE Ignore any references to stop1 low-power mode in this chapter, because the MC9S08AC16 Series does not support it. MC9S08AC16 Series Data Sheet, Rev.
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10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC1) HCS08 CORE IRQ/TPMCLK CPU PTA7 PTA2 PTA1 PTA0 PTB3/AD1P3 PTB2/AD1P2 PTB1/TPM3CH1/AD1P1 PTB0/TPM3CH0/AD1P0 SDA1 IIC MODULE (IIC1) SCL1 INTERNAL CLOCK GENERATOR (ICG) EXTAL XTAL HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT PORT C RESET 4 AD1P11–AD1P8 DEBUG MODULE (DBG) BKGD/MS BDC 4 AD1P3–AD1P0 PORT A VDDAD VSSAD VREFL VREFH PORT B Chapter 13 Inter-Integrated Circuit (S08IICV2) PTC5/RxD2 PTC4 PTC3/TxD2 PTC2/MCLK PT
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Inter-Integrated Circuit (S08IICV2) 13.1.
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Inter-Integrated Circuit (S08IICV2) Address Data Bus Interrupt ADDR_DECODE CTRL_REG DATA_MUX FREQ_REG ADDR_REG STATUS_REG DATA_REG Input Sync Start Stop Arbitration Control Clock Control In/Out Data Shift Register Address Compare SCL SDA Figure 13-2. IIC Functional Block Diagram 13.2 External Signal Description This section describes each user-accessible pin signal. 13.2.1 SCL — Serial Clock Line The bidirectional SCL is the serial clock line of the IIC system. 13.2.
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Inter-Integrated Circuit (S08IICV2) Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 13.3.1 IIC Address Register (IIC1A) 7 6 5 4 3 2 1 AD7 AD6 AD5 AD4 AD3 AD2 AD1 0 0 0 0 0 0 0 R 0 0 W Reset 0 = Unimplemented or Reserved Figure 13-3. IIC Address Register (IIC1A) Table 13-1. IIC1A Field Descriptions Field Description 7–1 AD[7:1] Slave Address.
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Inter-Integrated Circuit (S08IICV2) Table 13-2. IIC1F Field Descriptions Field 7–6 MULT 5–0 ICR Description IIC Multiplier Factor. The MULT bits define the multiplier factor, mul. This factor, along with the SCL divider, generates the IIC baud rate. The multiplier factor mul as defined by the MULT bits is provided below. 00 mul = 01 01 mul = 02 10 mul = 04 11 Reserved IIC Clock Rate. The ICR bits are used to prescale the bus clock for bit rate selection.
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Inter-Integrated Circuit (S08IICV2) Table 13-4.
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Inter-Integrated Circuit (S08IICV2) 13.3.3 IIC Control Register (IIC1C1) 7 6 5 4 3 IICEN IICIE MST TX TXAK R W Reset 2 1 0 0 0 0 0 0 RSTA 0 0 0 0 0 0 = Unimplemented or Reserved Figure 13-5. IIC Control Register (IIC1C1) Table 13-5. IIC1C1 Field Descriptions Field Description 7 IICEN IIC Enable. The IICEN bit determines whether the IIC module is enabled. 0 IIC is not enabled 1 IIC is enabled 6 IICIE IIC Interrupt Enable.
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Inter-Integrated Circuit (S08IICV2) Table 13-6. IIC1S Field Descriptions Field Description 7 TCF Transfer Complete Flag. This bit is set on the completion of a byte transfer. This bit is only valid during or immediately following a transfer to the IIC module or from the IIC module.The TCF bit is cleared by reading the IIC1D register in receive mode or writing to the IIC1D in transmit mode. 0 Transfer in progress 1 Transfer complete 6 IAAS Addressed as a Slave.
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Inter-Integrated Circuit (S08IICV2) Table 13-7. IIC1D Field Descriptions Field Description 7–0 DATA Data — In master transmit mode, when data is written to the IIC1D, a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data.
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Inter-Integrated Circuit (S08IICV2) 13.4 Functional Description This section provides a complete functional description of the IIC module. 13.4.1 IIC Protocol The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices connected to it must have open drain or open collector outputs. A logic AND function is exercised on both lines with external pull-up resistors. The value of these resistors is system dependent.
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Inter-Integrated Circuit (S08IICV2) 13.4.1.2 Slave Address Transmission The first byte of data transferred immediately after the start signal is the slave address transmitted by the master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired direction of data transfer. 1 = Read transfer, the slave transmits data to the master. 0 = Write transfer, the master transmits data to the slave.
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Inter-Integrated Circuit (S08IICV2) 13.4.1.5 Repeated Start Signal As shown in Figure 13-9, a repeated start signal is a start signal generated without first generating a stop signal to terminate the communication. This is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus. 13.4.1.6 Arbitration Procedure The IIC bus is a true multi-master bus that allows more than one master to be connected on it.
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Inter-Integrated Circuit (S08IICV2) 13.4.1.8 Handshaking The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold the SCL low after completion of one byte transfer (9 bits). In such a case, it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line. 13.4.1.9 Clock Stretching The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer.
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Inter-Integrated Circuit (S08IICV2) After a repeated start condition (Sr), all other slave devices also compare the first seven bits of the first byte of the slave address with their own addresses and test the eighth (R/W) bit. However, none of them are addressed because R/W = 1 (for 10-bit devices) or the 11110XX slave address (for 7-bit devices) does not match.
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Inter-Integrated Circuit (S08IICV2) 13.6.2 Address Detect Interrupt When the calling address matches the programmed slave address (IIC address register) or when the GCAEN bit is set and a general call is received, the IAAS bit in the status register is set. The CPU is interrupted, provided the IICIE is set. The CPU must check the SRW bit and set its Tx mode accordingly. 13.6.3 Arbitration Lost Interrupt The IIC is a true multi-master bus that allows more than one master to be connected on it.
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Inter-Integrated Circuit (S08IICV2) 13.7 Initialization/Application Information Module Initialization (Slave) 1. Write: IICC2 — to enable or disable general call — to select 10-bit or 7-bit addressing mode 2. Write: IICA — to set the slave address 3. Write: IICC1 — to enable IIC and interrupts 4. Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data 5. Initialize RAM variables used to achieve the routine shown in Figure 13-12 Module Initialization (Master) 1.
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Inter-Integrated Circuit (S08IICV2) Clear IICIF Master Mode ? Y TX N Arbitration Lost ? Y RX Tx/Rx ? N Last Byte Transmitted ? N Clear ARBL Y RXAK=0 ? Last Byte to Be Read ? N N N Y Y IAAS=1 ? Y IAAS=1 ? Y Address Transfer See Note 1 Y End of Addr Cycle (Master Rx) ? Y Y (Read) 2nd Last Byte to Be Read ? N SRW=1 ? Write Next Byte to IICD Set TXACK =1 TX/RX ? Generate Stop Signal (MST = 0) Y Set TX Mode RX TX N (Write) N N Data Transfer See Note 2 ACK from Receiver ?
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Chapter 14 Analog-to-Digital Converter (S08ADC10V1) 14.1 Overview The 10-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation within an integrated microcontroller system-on-chip. The ADC module design supports up to 28 separate analog inputs (AD0-AD27). Only 9 (AD0-AD3, AD8-AD11, and AD27) of the possible inputs are implemented on the MC9S08AC16 Series Family of MCUs. These inputs are selected by the ADCH bits.
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Chapter 14 Analog-to-Digital Converter (S08ADC10V1) Table 14-1. ADC Channel Assignment (continued) ADCH Channel Input Pin Control ADCH Channel Input Pin Control 01111 AD15 VREFL N/A 11111 module disabled None N/A NOTE Selecting the internal bandgap channel requires BGBE =1 in SPMSC1 see Section 5.9.8, “System Power Management Status and Control 1 Register (SPMSC1).” For value of bandgap voltage reference see Section A.6, “DC Characteristics.” 14.2.
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Chapter 14 Analog-to-Digital Converter (S08ADC10V1) 14.2.2.2 Low-Power Mode Operation The ADC is capable of running in stop3 mode but requires LVDSE and LVDE in SPMSC1 to be set. 14.2.3 Temperature Sensor The ADC1 module includes a temperature sensor whose output is connected to one of the ADC analog channel inputs. Equation 14-1 provides an approximate transfer function of the temperature sensor. Temp = 25 - ((VTEMP -VTEMP25)  m) Eqn.
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10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC1) HCS08 CORE IRQ/TPMCLK CPU PTA7 PTA2 PTA1 PTA0 PTB3/AD1P3 PTB2/AD1P2 PTB1/TPM3CH1/AD1P1 PTB0/TPM3CH0/AD1P0 SDA1 IIC MODULE (IIC1) SCL1 INTERNAL CLOCK GENERATOR (ICG) EXTAL XTAL HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT PORT C RESET 4 AD1P11–AD1P8 DEBUG MODULE (DBG) BKGD/MS BDC 4 AD1P3–AD1P0 PORT A VDDAD VSSAD VREFL VREFH PORT B Chapter 14 Analog-to-Digital Converter (S08ADC10V1) PTC5/RxD2 PTC4 PTC3/TxD2 PTC2/MC
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Analog-to-Digital Converter (S08ADC10V1) 14.2.4 Features Features of the ADC module include: • Linear successive approximation algorithm with 10 bits resolution. • Up to 28 analog inputs. • Output formatted in 10- or 8-bit right-justified format. • Single or continuous conversion (automatic return to idle after single conversion). • Configurable sample time and conversion speed/power. • Conversion complete flag and interrupt. • Input clock selectable from up to four sources.
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Analog-to-Digital Converter (S08ADC10V1) ADIV ADLPC MODE ADLSMP ADTRG 2 ADCO ADCH 1 ADC1CFG complete COCO ADC1SC1 ADICLK Compare true AIEN 3 Async Clock Gen ADACK MCU STOP ADCK  ALTCLK abort transfer sample initialize ••• AD0 convert Control Sequencer ADHWT Bus Clock Clock Divide AIEN 1 COCO 2 ADVIN Interrupt SAR Converter AD27 VREFH Data Registers Sum VREFL Compare true 3 Compare Value Registers ACFGT Value Compare Logic ADC1SC2 Figure 14-2.
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Analog-to-Digital Converter (S08ADC10V1) 14.3.1 Analog Power (VDDAD) The ADC analog portion uses VDDAD as its power connection. In some packages, VDDAD is connected internally to VDD. If externally available, connect the VDDAD pin to the same voltage potential as VDD. External filtering may be necessary to ensure clean VDDAD for good results. 14.3.2 Analog Ground (VSSAD) The ADC analog portion uses VSSAD as its ground connection. In some packages, VSSAD is connected internally to VSS.
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Analog-to-Digital Converter (S08ADC10V1) 7 R 6 5 4 AIEN ADCO 0 0 3 2 1 0 1 1 COCO ADCH W Reset: 0 1 1 1 = Unimplemented or Reserved Figure 14-3. Status and Control Register (ADC1SC1) Table 14-3. ADC1SC1 Register Field Descriptions Field Description 7 COCO Conversion Complete Flag — The COCO flag is a read-only bit which is set each time a conversion is completed when the compare function is disabled (ACFE = 0).
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Analog-to-Digital Converter (S08ADC10V1) Figure 14-4. Input Channel Select (continued) 14.4.
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Analog-to-Digital Converter (S08ADC10V1) Table 14-4. ADC1SC2 Register Field Descriptions (continued) Field Description 5 ACFE Compare Function Enable — ACFE is used to enable the compare function. 0 Compare function disabled 1 Compare function enabled 4 ACFGT Compare Function Greater Than Enable — ACFGT is used to configure the compare function to trigger when the result of the conversion of the input being monitored is greater than or equal to the compare value.
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Analog-to-Digital Converter (S08ADC10V1) R 7 6 5 4 3 2 1 0 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 0 0 0 0 0 0 0 0 W Reset: = Unimplemented or Reserved Figure 14-7. Data Result Low Register (ADC1RL) 14.4.5 Compare Value High Register (ADC1CVH) This register holds the upper two bits of the 10-bit compare value. These bits are compared to the upper two bits of the result following a conversion in 10-bit mode when the compare function is enabled.
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Analog-to-Digital Converter (S08ADC10V1) 7 6 5 4 3 2 1 0 R ADLPC ADIV ADLSMP MODE ADICLK W Reset: 0 0 0 0 0 0 0 0 Figure 14-10. Configuration Register (ADC1CFG) Table 14-5. ADC1CFG Register Field Descriptions Field Description 7 ADLPC Low Power Configuration — ADLPC controls the speed and power configuration of the successive approximation converter. This is used to optimize power consumption when higher sample rates are not required.
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Analog-to-Digital Converter (S08ADC10V1) Table 14-8. Input Clock Select ADICLK 00 14.4.8 Selected Clock Source Bus clock 01 Bus clock divided by 2 10 Alternate clock (ALTCLK) 11 Asynchronous clock (ADACK) Pin Control 1 Register (APCTL1) The pin control registers are used to disable the I/O port control of MCU pins used as analog inputs. APCTL1 is used to control the pins associated with channels 0–7 of the ADC module.
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Analog-to-Digital Converter (S08ADC10V1) Table 14-9. APCTL1 Register Field Descriptions (continued) Field Description 1 ADPC1 ADC Pin Control 1 — ADPC1 is used to control the pin associated with channel AD1. 0 AD1 pin I/O control enabled 1 AD1 pin I/O control disabled 0 ADPC0 ADC Pin Control 0 — ADPC0 is used to control the pin associated with channel AD0. 0 AD0 pin I/O control enabled 1 AD0 pin I/O control disabled 14.4.
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Analog-to-Digital Converter (S08ADC10V1) Table 14-10. APCTL2 Register Field Descriptions (continued) Field Description 1 ADPC9 ADC Pin Control 9 — ADPC9 is used to control the pin associated with channel AD9. 0 AD9 pin I/O control enabled 1 AD9 pin I/O control disabled 0 ADPC8 ADC Pin Control 8 — ADPC8 is used to control the pin associated with channel AD8. 0 AD8 pin I/O control enabled 1 AD8 pin I/O control disabled 14.4.
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Analog-to-Digital Converter (S08ADC10V1) Table 14-11. APCTL3 Register Field Descriptions (continued) Field Description 1 ADPC17 ADC Pin Control 17 — ADPC17 is used to control the pin associated with channel AD17. 0 AD17 pin I/O control enabled 1 AD17 pin I/O control disabled 0 ADPC16 ADC Pin Control 16 — ADPC16 is used to control the pin associated with channel AD16. 0 AD16 pin I/O control enabled 1 AD16 pin I/O control disabled 14.
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Analog-to-Digital Converter (S08ADC10V1) are too fast, then the clock must be divided to the appropriate frequency. This divider is specified by the ADIV bits and can be divide-by 1, 2, 4, or 8. 14.5.2 Input Select and Pin Control The pin control registers (APCTL3, APCTL2, and APCTL1) are used to disable the I/O port control of the pins used as analog inputs.
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Analog-to-Digital Converter (S08ADC10V1) 14.5.4.2 Completing Conversions A conversion is completed when the result of the conversion is transferred into the data result registers, ADC1RH and ADC1RL. This is indicated by the setting of COCO. An interrupt is generated if AIEN is high at the time that COCO is set.
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Analog-to-Digital Converter (S08ADC10V1) result of the conversion is transferred to ADC1RH and ADC1RL upon completion of the conversion algorithm. If the bus frequency is less than the fADCK frequency, precise sample time for continuous conversions cannot be guaranteed when short sample is enabled (ADLSMP=0). If the bus frequency is less than 1/11th of the fADCK frequency, precise sample time for continuous conversions cannot be guaranteed when long sample is enabled (ADLSMP=1).
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Analog-to-Digital Converter (S08ADC10V1) 14.5.5 Automatic Compare Function The compare function can be configured to check for either an upper limit or lower limit. After the input is sampled and converted, the result is added to the two’s complement of the compare value (ADC1CVH and ADC1CVL). When comparing to an upper limit (ACFGT = 1), if the result is greater-than or equal-to the compare value, COCO is set.
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Analog-to-Digital Converter (S08ADC10V1) 14.5.7.2 Stop3 Mode With ADACK Enabled If ADACK is selected as the conversion clock, the ADC continues operation during stop3 mode. For guaranteed ADC operation, the MCU’s voltage regulator must remain active during stop3 mode. Consult the module introduction for configuration information for this MCU. If a conversion is in progress when the MCU enters stop3 mode, it continues until completion.
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Analog-to-Digital Converter (S08ADC10V1) 2. Update status and control register 2 (ADCSC2) to select the conversion trigger (hardware or software) and compare function options, if enabled. 3. Update status and control register 1 (ADCSC1) to select whether conversions will be continuous or completed only once, and to enable or disable conversion complete interrupts. The input channel on which conversions will be performed is also selected here. 14.6.1.
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Analog-to-Digital Converter (S08ADC10V1) RESET INITIALIZE ADC ADCCFG = $98 ADCSC2 = $00 ADCSC1 = $41 CHECK COCO=1? NO YES READ ADCRH THEN ADCRL TO CLEAR COCO BIT CONTINUE Figure 14-14. Initialization Flowchart for Example 14.7 Application Information This section contains information for using the ADC module in applications. The ADC has been designed to be integrated into a microcontroller for use in embedded control applications requiring an A/D converter. 14.7.
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Analog-to-Digital Converter (S08ADC10V1) In cases where separate power supplies are used for analog and digital power, the ground connection between these supplies must be at the VSSAD pin. This should be the only ground connection between these supplies if possible. The VSSAD pin makes a good single point ground location. 14.7.1.2 Analog Reference Pins In addition to the analog supplies, the ADC module has connections for two reference voltage inputs.
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Analog-to-Digital Converter (S08ADC10V1) 14.7.2 Sources of Error Several sources of error exist for A/D conversions. These are discussed in the following sections. 14.7.2.1 Sampling Error For proper conversions, the input must be sampled long enough to achieve the proper accuracy. Given the maximum input resistance of approximately 7k and input capacitance of approximately 5.5 pF, sampling to within 1/4LSB (at 10-bit resolution) can be achieved within the minimum sample window (3.
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Analog-to-Digital Converter (S08ADC10V1) • • Average the result by converting the analog input many times in succession and dividing the sum of the results. Four samples are required to eliminate the effect of a 1LSB, one-time error. Reduce the effect of synchronous noise by operating off the asynchronous clock (ADACK) and averaging. Noise that is synchronous to ADCK cannot be averaged out. 14.7.2.
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Analog-to-Digital Converter (S08ADC10V1) converter yields the lower code (and vice-versa). However, even very small amounts of system noise can cause the converter to be indeterminate (between two codes) for a range of input voltages around the transition voltage. This range is normally around ±1/2 LSB and will increase with noise. This error may be reduced by repeatedly sampling the input and averaging the result. Additionally the techniques discussed in Section 14.7.2.3 will reduce this error.
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Analog-to-Digital Converter (S08ADC10V1) MC9S08AC16 Series Data Sheet, Rev.
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Chapter 15 Development Support 15.1 Introduction Development support systems in the HCS08 include the background debug controller (BDC) and the on-chip debug module (DBG). The BDC provides a single-wire debug interface to the target MCU that provides a convenient interface for programming the on-chip FLASH and other nonvolatile memories.
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Development Support 15.1.
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Development Support • Non-intrusive commands can be executed at any time even while the user’s program is running. Non-intrusive commands allow a user to read or write MCU memory locations or access status and control registers within the background debug controller. Typically, a relatively simple interface pod is used to translate commands from a host computer into commands for the custom serial interface to the single-wire background debug system.
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Development Support When no debugger pod is connected to the 6-pin BDM interface connector, the internal pullup on BKGD chooses normal operating mode. When a debug pod is connected to BKGD it is possible to force the MCU into active background mode after reset. The specific conditions for forcing active background depend upon the HCS08 derivative (refer to the introduction to this Development Support section).
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Development Support Figure 15-2 shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target HCS08 MCU. The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target senses the bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD pin during host-to-target transmissions to speed up rising edges.
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Development Support Figure 15-3 shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long enough for the target to recognize it (at least two target BDC cycles).
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Development Support Figure 15-4 shows the host receiving a logic 0 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the target HCS08 finishes it.
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Development Support 15.2.3 BDC Commands BDC commands are sent serially from a host computer to the BKGD pin of the target HCS08 MCU. All commands and data are sent MSB-first using a custom BDC communications protocol. Active background mode commands require that the target MCU is currently in the active background mode while non-intrusive commands may be issued at any time whether the target MCU is in active background mode or running a user application program.
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Development Support Table 15-1. BDC Command Summary Command Mnemonic 1 Active BDM/ Non-intrusive Coding Structure Description SYNC Non-intrusive n/a1 Request a timed reference pulse to determine target BDC communication speed ACK_ENABLE Non-intrusive D5/d Enable acknowledge protocol. Refer to document order no. HCS08RMv1/D. ACK_DISABLE Non-intrusive D6/d Disable acknowledge protocol. Refer to document order no. HCS08RMv1/D.
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Development Support The SYNC command is unlike other BDC commands because the host does not necessarily know the correct communications speed to use for BDC communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host: • Drives the BKGD pin low for at least 128 cycles of the slowest possible BDC clock (The slowest clock is normally the reference oscillator/64 or the self-clocked rate/64.
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Development Support 15.3 On-Chip Debug System (DBG) Because HCS08 devices do not have external address and data buses, the most important functions of an in-circuit emulator have been built onto the chip with the MCU. The debug system consists of an 8-stage FIFO that can store address or data bus information, and a flexible trigger system to decide when to capture bus information and what information to capture.
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Development Support the host must perform ((8 – CNT) – 1) dummy reads of the FIFO to advance it to the first significant entry in the FIFO. In most trigger modes, the information stored in the FIFO consists of 16-bit change-of-flow addresses. In these cases, read DBGFH then DBGFL to get one coherent word of information out of the FIFO. Reading DBGFL (the low-order byte of the FIFO data port) causes the FIFO to shift so the next word of information is available at the FIFO data port.
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Development Support A force-type breakpoint waits for the current instruction to finish and then acts upon the breakpoint request. The usual action in response to a breakpoint is to go to active background mode rather than continuing to the next instruction in the user application program. The tag vs. force terminology is used in two contexts within the debug module. The first context refers to breakpoint requests from the debug module to the CPU.
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Development Support A-Only — Trigger when the address matches the value in comparator A A OR B — Trigger when the address matches either the value in comparator A or the value in comparator B A Then B — Trigger when the address matches the value in comparator B but only after the address for another cycle matched the value in comparator A. There can be any number of cycles after the A match and before the B match.
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Development Support 15.3.6 Hardware Breakpoints The BRKEN control bit in the DBGC register may be set to 1 to allow any of the trigger conditions described in Section 15.3.5, “Trigger Modes,” to be used to generate a hardware breakpoint request to the CPU. TAG in DBGC controls whether the breakpoint request will be treated as a tag-type breakpoint or a force-type breakpoint. A tag breakpoint causes the current opcode to be marked as it enters the instruction queue.
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Development Support 15.4.1.1 BDC Status and Control Register (BDCSCR) This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL) but is not accessible to user programs because it is not located in the normal memory map of the MCU. 7 R 6 5 4 3 BKPTEN FTS CLKSW BDMACT ENBDM 2 1 0 WS WSF DVF W Normal Reset 0 0 0 0 0 0 0 0 Reset in Active BDM: 1 1 0 0 1 0 0 0 = Unimplemented or Reserved Figure 15-5.
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Development Support Table 15-2. BDCSCR Register Field Descriptions (continued) Field Description 2 WS Wait or Stop Status — When the target CPU is in wait or stop mode, most BDC commands cannot function. However, the BACKGROUND command can be used to force the target CPU out of wait or stop and into active background mode where all BDC commands work.
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Development Support R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 BDFR1 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved 1 BDFR is writable only through serial background mode debug commands, not from user programs. Figure 15-6. System Background Debug Force Reset Register (SBDFR) Table 15-3.
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Development Support 15.4.3.5 Debug FIFO High Register (DBGFH) This register provides read-only access to the high-order eight bits of the FIFO. Writes to this register have no meaning or effect. In the event-only trigger modes, the FIFO only stores data into the low-order byte of each FIFO word, so this register is not used and will read 0x00. Reading DBGFH does not cause the FIFO to shift to the next word.
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Development Support 15.4.3.7 Debug Control Register (DBGC) This register can be read or written at any time. 7 6 5 4 3 2 1 0 DBGEN ARM TAG BRKEN RWA RWAEN RWB RWBEN 0 0 0 0 0 0 0 0 R W Reset Figure 15-7. Debug Control Register (DBGC) Table 15-4. DBGC Register Field Descriptions Field Description 7 DBGEN Debug Module Enable — Used to enable the debug module. DBGEN cannot be set to 1 if the MCU is secure.
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Development Support 15.4.3.8 Debug Trigger Register (DBGT) This register can be read any time, but may be written only if ARM = 0, except bits 4 and 5 are hard-wired to 0s. 7 6 TRGSEL BEGIN 0 0 R 5 4 0 0 3 2 1 0 TRG3 TRG2 TRG1 TRG0 0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 15-8. Debug Trigger Register (DBGT) Table 15-5.
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Development Support 15.4.3.9 Debug Status Register (DBGS) This is a read-only status register. R 7 6 5 4 3 2 1 0 AF BF ARMF 0 CNT3 CNT2 CNT1 CNT0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 15-9. Debug Status Register (DBGS) Table 15-6. DBGS Register Field Descriptions Field Description 7 AF Trigger Match A Flag — AF is cleared at the start of a debug run and indicates whether a trigger match A condition was met since arming.
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Appendix A Electrical Characteristics and Timing Specifications A.1 Introduction This section contains electrical and timing specifications. A.2 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the following classification is used and the parameters are tagged accordingly in the tables where appropriate: Table A-1.
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Appendix A Electrical Characteristics and Timing Specifications maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD). Table A-2. Absolute Maximum Ratings Rating Symbol Value Unit Supply voltage VDD –0.3 to + 5.8 V Input voltage VIn – 0.3 to VDD + 0.
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Appendix A Electrical Characteristics and Timing Specifications VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table A-3.
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Appendix A Electrical Characteristics and Timing Specifications A.5 ESD Protection and Latch-Up Immunity Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
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Appendix A Electrical Characteristics and Timing Specifications A.6 DC Characteristics This section includes information about power supply requirements, I/O pin characteristics, and power supply current in various operating modes. Table A-6. DC Characteristics Num C Parameter Symbol Output high voltage — Low Drive (PTxDSn = 0) 5 V, ILoad = –2 mA 3 V, ILoad = –0.6 mA 5 V, ILoad = –0.4 mA 3 V, ILoad = –0.
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Appendix A Electrical Characteristics and Timing Specifications Table A-6. DC Characteristics (continued) Symbol Min Typ1 Max Unit P Low-voltage detection threshold — high range VDD falling VDD rising VLVDH 4.2 4.3 4.3 4.4 4.4 4.5 V Num C 15 Parameter 16 P Low-voltage detection threshold — low range VDD falling VDD rising VLVDL 2.48 2.54 2.56 2.62 2.64 2.7 V 17 P Low-voltage warning threshold — high range VDD falling VDD rising VLVWH 4.2 4.3 4.3 4.4 4.4 4.
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Appendix A Electrical Characteristics and Timing Specifications VDD–VOH (V) Average of IOH –6.0E-3 –5.0E-3 –40C 25C 125C IOH (A) –4.0E-3 –3.0E-3 –2.0E-3 –1.0E-3 000E+0 0 0.3 0.5 0.8 VSupply–VOH 0.9 1.2 1.5 Figure A-1. Typical IOH (Low Drive) vs VDD–VOH at VDD = 3 V –20.0E-3 VDD–VOH (V) Average of IOH –18.0E-3 –16.0E-3 –14.0E-3 –12.0E-3 –10.0E-3 –8.0E-3 –6.0E-3 –4.0E-3 –2.0E-3 000.0E-3 IOH (A) –40C 25C 125C 0 0.3 0.5 0.8 VSupply–VOH 0.9 1.2 1.5 Figure A-2.
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Appendix A Electrical Characteristics and Timing Specifications Average of IOH –7.0E-3 –40C 25C 125C –6.0E-3 –5.0E-3 IOH (A) –4.0E-3 –3.0E-3 –2.0E-3 –1.0E-3 000E+0 0.00 0.30 0.50 0.80 1.00 1.30 2.00 VDD–VOH (V) VSupply–VOH Figure A-3. Typical IOH (Low Drive) vs VDD–VOH at VDD = 5 V VDD–VOH (V) Average of IOH –30.0E-3 –25.0E-3 –40C 25C 125C –20.0E-3 IOH (A) –15.0E-3 –10.0E-3 –5.0E-3 000.0E+3 0.00 0.30 0.50 0.80 1.00 1.30 2.00 VSupply–VOH Figure A-4.
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Appendix A Electrical Characteristics and Timing Specifications A.7 Supply Current Characteristics Table A-7.
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Appendix A Electrical Characteristics and Timing Specifications 18 20 MHz, ADC off, FEE, 25C 16 20 MHz, ADC off, FBE, 25C 14 12 10 IDD 8 8 MHz, ADC off, FEE, 25C 8 MHz, ADC off, FBE, 25C 6 4 1 MHz, ADC off, FEE, 25C 1 MHz, ADC off, FBE, 25C 2 0 2.2 2.6 3.0 3.4 3.8 4.2 4.6 5.0 5.4 VDD Note: External clock is square wave supplied by function generator. For FEE mode, external reference frequency is 4 Figure A-5. Typical Run IDD for FBE and FEE Modes, IDD vs.
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Appendix A Electrical Characteristics and Timing Specifications –40C 25C 55C 85C Stop2 IDD (A) –8.0E-3 Average of Measurement IDD –7.0E-3 –6.0E-3 IDD (A) –5.0E-3 –4.0E-3 –3.0E-3 –2.0E-3 –1.0E-3 000E+0 1.8 2 2.5 3 3.5 4 4.5 5 VDD (V) Figure A-6. Typical Stop2 IDD –40C 25C 55C 85C Stop3 IDD (A) –8.0E-3 Average of Measurement IDD –7.0E-3 –6.0E-3 IDD (A) –5.0E-3 –4.0E-3 –3.0E-3 –2.0E-3 –1.0E-3 000E+0 1.8 2 2.5 3 3.5 4 4.5 5 VDD (V) Figure A-7.
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Appendix A Electrical Characteristics and Timing Specifications A.8 ADC Characteristics Table A-8. 5 Volt 10-bit ADC Operating Conditions Symb Min Typ1 Max Unit Absolute VDDAD 2.7 — 5.5 V Delta to VDD (VDD–VDDAD)2 VDDAD –100 0 +100 mV Delta to VSS (VSS–VSSAD)2 VSSAD –100 0 +100 mV Ref voltage high VREFH 2.7 VDDAD VDDAD V Ref voltage low VREFL VSSAD VSSAD VSSAD V IDDAD — 0.011 1 A Input Voltage VADIN VREFL — VREFH V Input capacitance CADIN — 4.5 5.
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Appendix A Electrical Characteristics and Timing Specifications SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT Pad leakage due to input protection ZAS RAS ADC SAR ENGINE RADIN + VADIN VAS CAS + – – RADIN INPUT PIN RADIN INPUT PIN RADIN INPUT PIN CADIN Figure A-8. ADC Input Impedance Equivalency Diagram Table A-9.
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Appendix A Electrical Characteristics and Timing Specifications Table A-9. 5 Volt 10-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued) Conditions C Symb Min Typ1 Max Unit Short sample (ADLSMP = 0) P tADS — 3.5 — — 23.5 — ADCK cycles — 1 2.5 — 0.5 1.0 — 0.5 1.0 — 0.3 0.
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Appendix A Electrical Characteristics and Timing Specifications A.9 Internal Clock Generation Module Characteristics ICG EXTAL XTAL RS RF Crystal or Resonator C1 C2 Table A-10.
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Appendix A Electrical Characteristics and Timing Specifications A.9.1 ICG Frequency Specifications Table A-11.
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Appendix A Electrical Characteristics and Timing Specifications Table A-11. ICG Frequency Specifications (continued) (VDDA = VDDA (min) to VDDA (max), Temperature Range = –40 to 125C Ambient) Num C Characteristic MC9S08ACxx: Internal oscillator deviation from trimmed frequency9 VDD = 2.7 – 5.5 V, (constant temperature) VDD = 5.0 V 10%, –40 C to 125C 18 S9S08AWxxA: Internal oscillator deviation from trimmed frequency10 VDD = 2.7 – 5.5 V, (constant temperature) C P VDD = 5.
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Appendix A Electrical Characteristics and Timing Specifications Internal Oscillator Deviation from Trimmed Frequency Variable 5V 3V 0.0 Percent (%) –0.5 –1.0 –1.5 –2.0 –50 –25 0 25 50 Temp 75 100 125 Device trimmed at 25C at 3.0 V. Figure A-9. Typical Internal Oscillator Deviation from Trimmed Frequency MC9S08AC16 Series Data Sheet, Rev.
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Appendix A Electrical Characteristics and Timing Specifications A.10 AC Characteristics This section describes ac timing characteristics for each peripheral system. For detailed information about how clocks for the bus are generated, see Chapter 8, “Internal Clock Generator (S08ICGV4).” A.10.1 Control Timing Table A-12.
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Appendix A Electrical Characteristics and Timing Specifications BKGD/MS RESET tMSH tMSSU Figure A-11. Active Background Debug Mode Latch Timing tIHIL IRQ/KBIP6–KBIP4 IRQ/KBIPx tILIH Figure A-12. IRQ/KBIPx Timing A.10.2 Timer/PWM (TPM) Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table A-13.
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Appendix A Electrical Characteristics and Timing Specifications tTPMext tclkh TPMxCLK tclkl Figure A-13. Timer External Clock tICPW TPMxCHn TPMxCHn tICPW Figure A-14. Timer Input Capture Pulse MC9S08AC16 Series Data Sheet, Rev.
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Appendix A Electrical Characteristics and Timing Specifications A.11 SPI Characteristics Table A-14 and Figure A-15 through Figure A-18 describe the timing requirements for the SPI system. Table A-14.
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Appendix A Electrical Characteristics and Timing Specifications SS1 (OUTPUT) 3 1 2 SCK (CPOL = 0) (OUTPUT) 5 4 SCK (CPOL = 1) (OUTPUT) 5 4 6 MISO (INPUT) 7 MSB IN2 BIT 6 . . . 1 10 MOSI (OUTPUT) LSB IN 11 10 MSB OUT2 BIT 6 . . . 1 LSB OUT NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure A-15.
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Appendix A Electrical Characteristics and Timing Specifications SS (INPUT) 3 1 SCK (CPOL = 0) (INPUT) 5 4 2 SCK (CPOL = 1) (INPUT) 5 4 8 MISO (OUTPUT) 11 10 BIT 6 . . . 1 MSB OUT SLAVE SLAVE LSB OUT SEE NOTE 7 6 MOSI (INPUT) 9 BIT 6 . . . 1 MSB IN LSB IN NOTE: 1. Not defined but normally MSB of character just received Figure A-17.
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Appendix A Electrical Characteristics and Timing Specifications Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see Chapter 4, “Memory.” Table A-15. FLASH Characteristics Num C Characteristic Symbol Min Typ1 Max Unit 1 Supply voltage for program/erase Vprog/erase 2.7 5.5 V 2 Supply voltage for read operation VRead 2.7 5.
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Appendix A Electrical Characteristics and Timing Specifications MC9S08AC16 Series Data Sheet, Rev.
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Appendix B Ordering Information and Mechanical Drawings B.1 Ordering Information This section contains ordering information for the MC9S08AC16 Series devices. See below for an example of the device numbering system. Table B-1.
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Appendix B Ordering Information and Mechanical Drawings B.2 Orderable Part Numbering System The orderable part numbers for the MC9S08AC16 Series devices varies according to the device family. Refer to Figure B-1 and Figure B-2 for examples. MC 9 S08 AC n C xx E Pb Free Indicator - E = Pb Free Status - MC = Consumer & Industrial Package Designator Two letter descriptor (refer to Table B-2).
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Appendix B Ordering Information and Mechanical Drawings B.3 Mechanical Drawings This following pages contain mechanical specifications for MC9S08AC16 Series package options. See the following tables for the document numbers that correspond to each package type. Table B-2. MC9S08AC16 and MC9S08AC8 Consumer & Industrial Package Information Pin Count Type Designator Document No. 48 QFN FD 98ARH99048A 44 LQFP FG 98ASS23225W 42 SDIP B 98ASB42767B 32 LQFP FJ 98ASH70029A Table B-3.
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Appendix B Ordering Information and Mechanical Drawings MC9S08AC16 Series Data Sheet, Rev.
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