Datasheet

Chapter 6 Parallel Input/Output
MC9S08AC16 Series Data Sheet, Rev. 9
Freescale Semiconductor 103
6.7.12 Port F Pin Control Registers (PTFPE, PTFSE, PTFDS)
In addition to the I/O control, port F pins are controlled by the registers listed below.
76543210
R
R PTFPE6 PTFPE5 PTFPE4 R R PTFPE1 PTFPE0
W
Reset00000000
Figure 6-37. Internal Pullup Enable for Port F (PTFPE)
1
1
Bits 7, 3 and 2 are reserved bits that must always be written to 0.
Table 6-28. PTFPE Register Field Descriptions
Field Description
6:4, 1:0
PTFPEn
Internal Pullup Enable for Port F Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTF pin. For port F pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port F bit n.
1 Internal pullup device enabled for port F bit n.
76543210
R
R PTFSE6 PTFSE5 PTFSE4 R R PTFSE1 PTFSE0
W
Reset00000000
Figure 6-38. Output Slew Rate Control Enable for Port F (PTFSE)
1
1
Bits 7, 3 and 2 are reserved bits that must always be written to 0.
Table 6-29. PTFSE Register Field Descriptions
Field Description
6:4, 1:0
PTFSEn
Output Slew Rate Control Enable for Port F Bits — Each of these control bits determine whether output slew
rate control is enabled for the associated PTF pin. For port F pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port F bit n.
1 Output slew rate control enabled for port F bit n.