Datasheet

Chapter 6 Parallel Input/Output
MC9S08AC16 Series Data Sheet, Rev. 9
104 Freescale Semiconductor
6.7.13 Port G I/O Registers (PTGD and PTGDD)
Port G parallel I/O function is controlled by the registers listed below.
76543210
R
R PTFDS6 PTFDS5 PTFDS4 R R PTFDS1 PTFDS0
W
Reset00000000
Figure 6-39. Output Drive Strength Selection for Port F (PTFDS)
1
1
Bits 7, 3 and 2 are reserved bits that must always be written to 0.
Table 6-30. PTFDS Register Field Descriptions
Field Description
6:4, 1:0
PTFDSn
Output Drive Strength Selection for Port F Bits — Each of these control bits selects between low and high
output drive for the associated PTF pin.
0 Low output drive enabled for port F bit n.
1 High output drive enabled for port F bit n.
76543210
R0
PTGD6 PTGD5 PTGD4 PTGD3 PTGD2 PTGD1 PTGD0
W
Reset00000000
Figure 6-40. Port G Data Register (PTGD)
Table 6-31. PTGD Register Field Descriptions
Field Description
6:0
PTGD[6:0]
Port G Data Register Bits — For port G pins that are inputs, reads return the logic level on the pin. For port G
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port G pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTGD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.