Datasheet

Chapter 6 Parallel Input/Output
MC9S08AC16 Series Data Sheet, Rev. 9
Freescale Semiconductor 105
6.7.14 Port G Pin Control Registers (PTGPE, PTGSE, PTGDS)
In addition to the I/O control, port G pins are controlled by the registers listed below.
76543210
R0
PTGDD6 PTGDD5 PTGDD4 PTGDD3 PTGDD2 PTGDD1 PTGDD0
W
Reset00000000
Figure 6-41. Data Direction for Port G (PTGDD)
Table 6-32. PTGDD Register Field Descriptions
Field Description
6:0
PTGDD[6:0]
Data Direction for Port G Bits — These read/write bits control the direction of port G pins and what is read for
PTGD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn.
76543210
R0
PTGPE6 PTGPE5 PTGPE4 PTGPE3 PTGPE2 PTGPE1 PTGPE0
W
Reset00000000
Figure 6-42. Internal Pullup Enable for Port G Bits (PTGPE)
Table 6-33. PTGPE Register Field Descriptions
Field Description
6:0
PTGPE[6:0]
Internal Pullup Enable for Port G Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTG pin. For port G pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port G bit n.
1 Internal pullup device enabled for port G bit n.