Datasheet

Chapter 10 Timer/PWM (S08TPMV3)
MC9S08AC16 Series Data Sheet, Rev. 9
Freescale Semiconductor 161
10.3 TPMV3 Differences from Previous Versions
The TPMV3 is the latest version of the Timer/PWM module that addresses errata found in previous
versions. The following section outlines the differences between TPMV3 and TPMV2 modules, and any
considerations that should be taken when porting code.
Table 10-1. TPMV2 and TPMV3 Porting Considerations
Action TPMV3 TPMV2
Write to TPMxCnTH:L registers
1
Any write to TPMxCNTH or TPMxCNTL registers Clears the TPM counter
(TPMxCNTH:L) and the
prescaler counter.
Clears the TPM counter
(TPMxCNTH:L) only.
Read of TPMxCNTH:L registers
1
In BDM mode, any read of TPMxCNTH:L registers Returns the value of the TPM
counter that is frozen.
If only one byte of the
TPMxCNTH:L registers was
read before the BDM mode
became active, returns the
latched value of TPMxCNTH:L
from the read buffer (instead of
the frozen TPM counter value).
In BDM mode, a write to TPMxSC, TPMxCNTH or TPMxCNTL Clears this read coherency
mechanism.
Does not clear this read
coherency mechanism.
Read of TPMxCnVH:L registers
2
In BDM mode, any read of TPMxCnVH:L registers Returns the value of the
TPMxCnVH:L register.
If only one byte of the
TPMxCnVH:L registers was
read before the BDM mode
became active, returns the
latched value of TPMxCNTH:L
from the read buffer (instead of
the value in the TPMxCnVH:L
registers).
In BDM mode, a write to TPMxCnSC Clears this read coherency
mechanism.
Does not clear this read
coherency mechanism.
Write to TPMxCnVH:L registers
In Input Capture mode, writes to TPMxCnVH:L registers
3
Not allowed. Allowed.
In Output Compare mode, when (CLKSB:CLKSA not = 0:0),
writes to TPMxCnVH:L registers
3
Update the TPMxCnVH:L
registers with the value of
their write buffer at the next
change of the TPM counter
(end of the prescaler
counting) after the second
byte is written.
Always update these registers
when their second byte is
written.