Datasheet

Chapter 5 Resets, Interrupts, and System Configuration
MC9S08AC16 Series Data Sheet, Rev. 9
Freescale Semiconductor 77
5.9.8 System Power Management Status and Control 1 Register (SPMSC1)
Table 5-11. Real-Time Interrupt Frequency
RTIS2:RTIS1:RTIS0 1-kHz Clock Source Delay
1
1
Normal values are shown in this column based on f
RTI
= 1 kHz. See Appendix A, “Electrical Characteristics and
Timing Specifications,” f
RTI
for the tolerance on these values.
Using External Clock Source Delay
(Crystal Frequency)
0:0:0 Disable periodic wakeup timer Disable periodic wakeup timer
0:0:1 8 ms divide by 256
0:1:0 32 ms divide by 1024
0:1:1 64 ms divide by 2048
1:0:0 128 ms divide by 4096
1:0:1 256 ms divide by 8192
1:1:0 512 ms divide by 16384
1:1:1 1.024 s divide by 32768
7654321
1
0
RLVDF 0
LVDIE LVDRE
2
LVD SE
2
LVDE
2
BGBE
W LV DACK
Reset00011100
= Unimplemented or Reserved
1
Bit 1 is a reserved bit that must always be written to 0.
2
This bit can be written only one time after reset. Additional writes are ignored.
Figure 5-10. System Power Management Status and Control 1 Register (SPMSC1)
Table 5-12. SPMSC1 Register Field Descriptions
Field Description
7
LVD F
Low-Voltage Detect Flag — Provided LVDE = 1, this read-only status bit indicates a low-voltage detect event.
6
LVDAC K
Low-Voltage Detect Acknowledge — This write-only bit is used to acknowledge low voltage detection errors
(write 1 to clear LVDF). Reads always return 0.
5
LVD IE
Low-Voltage Detect Interrupt Enable — This read/write bit enables hardware interrupt requests for LVDF.
0 Hardware interrupt disabled (use polling).
1 Request a hardware interrupt when LVDF = 1.
4
LVDRE
Low-Voltage Detect Reset Enable — This read/write bit enables LVDF events to generate a hardware reset
(provided LVDE = 1).
0 LVDF does not generate hardware resets.
1 Force an MCU reset when LVDF = 1.