Datasheet

Chapter 6 Parallel Input/Output
MC9S08AC16 Series Data Sheet, Rev. 9
Freescale Semiconductor 91
76543210
R
PTASE7 R R R R PTASE2 PTASE1 PTASE0
W
Reset00000000
Figure 6-13. Output Slew Rate Control Enable for Port A (PTASE)
1
1
Bits 6 through 3 are reserved bits that must always be written to 0.
Table 6-4. PTASE Register Field Descriptions
Field Description
7, 2:0
PTASEn
Output Slew Rate Control Enable for Port A Bits — Each of these control bits determine whether output slew
rate control is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.
76543210
R
PTADS7 R R R R PTADS2 PTADS1 PTADS0
W
Reset00000000
Figure 6-14. Output Drive Strength Selection for Port A (PTADS)
1
1
Bits 6 through 3 are reserved bits that must always be written to 0.
Table 6-5. PTADS Register Field Descriptions
Field Description
7, 2:0
PTADSn
Output Drive Strength Selection for Port A Bits — Each of these control bits selects between low and high
output drive for the associated PTA pin.
0 Low output drive enabled for port A bit n.
1 High output drive enabled for port A bit n.