Datasheet

Chapter 6 Parallel Input/Output
MC9S08AC16 Series Data Sheet, Rev. 9
Freescale Semiconductor 99
6.7.9 Port E I/O Registers (PTED and PTEDD)
Port E parallel I/O function is controlled by the registers listed below.
76543210
R
R R R R PTDDS3 PTDDS2 PTDDS1 PTDDS0
W
Reset00000000
Figure 6-29. Output Drive Strength Selection for Port D (PTDDS)
1
1
Bits 7 through 4 are reserved bits that must always be written to 0.
Table 6-20. PTDDS Register Field Descriptions
Field Description
3:0
PTDDS[3:0]
Output Drive Strength Selection for Port D Bits — Each of these control bits selects between low and high
output drive for the associated PTD pin.
0 Low output drive enabled for port D bit n.
1 High output drive enabled for port D bit n.
76543210
R
PTED7 PTED6 PTED5 PTED4 PTED3 PTED2 PTED1 PTED0
W
Reset00000000
Figure 6-30. Port E Data Register (PTED)
Table 6-21. PTED Register Field Descriptions
Field Description
7:0
PTED[7:0]
Port E Data Register Bits — For port E pins that are inputs, reads return the logic level on the pin. For port E
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port E pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTED to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.