MC9S08AW60 MC9S08AW48 MC9S08AW32 MC9S08AW16 Data Sheet HCS08 Microcontrollers MC9S08AW60 Rev 2 12/2006 freescale.
MC9S08AW60 Features 8-Bit HCS08 Central Processor Unit (CPU) • • • • • • • 40-MHz HCS08 CPU (central processor unit) 20-MHz internal bus frequency HC08 instruction set with added BGND instruction Single-wire background debug mode interface Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) On-chip real-time in-circuit emulation (ICE) with two comparators (plus one in BDM), nine trigger modes, and on-chip bus capture buf
MC9S08AW60 Data Sheet Covers: MC9S08AW60 MC9S08AW48 MC9S08AW32 MC9S08AW16 MC9S08AW60 Rev 2 12/2006
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List of Chapters Chapter Title Page Chapter 1 Introduction...................................................................................... 19 Chapter 2 Pins and Connections ..................................................................... 23 Chapter 3 Modes of Operation ......................................................................... 33 Chapter 4 Memory .............................................................................................
Contents Section Number Title Page Chapter 1 Introduction 1.1 1.2 1.3 Overview .........................................................................................................................................19 MCU Block Diagrams .....................................................................................................................19 System Clock Distribution ..............................................................................................................
Section Number 4.4 4.5 4.6 Title Page FLASH ............................................................................................................................................50 4.4.1 Features ...........................................................................................................................51 4.4.2 Program and Erase Times ...............................................................................................51 4.4.3 Program and Erase Command Execution ..........
Section Number 5.9.8 5.9.9 Title Page System Power Management Status and Control 1 Register (SPMSC1) .........................79 System Power Management Status and Control 2 Register (SPMSC2) .........................80 Chapter 6 Parallel Input/Output 6.1 6.2 6.3 6.4 6.5 6.6 6.7 Introduction .....................................................................................................................................81 Features ...................................................................
Section Number 7.3 7.4 7.5 Title Page 7.2.1 Accumulator (A) ...........................................................................................................110 7.2.2 Index Register (H:X) ....................................................................................................110 7.2.3 Stack Pointer (SP) .........................................................................................................111 7.2.4 Program Counter (PC) ...........................................
Section Number 8.5 Title Page 8.4.4 FLL Engaged Internal Unlocked ..................................................................................143 8.4.5 FLL Engaged Internal Locked ......................................................................................143 8.4.6 FLL Bypassed, External Clock (FBE) Mode ...............................................................143 8.4.7 FLL Engaged, External Clock (FEE) Mode .................................................................143 8.4.
Section Number Title Page 10.4.3 Timer x Counter Modulo Registers (TPMxMODH:TPMxMODL) .............................172 10.4.4 Timer x Channel n Status and Control Register (TPMxCnSC) ....................................173 10.4.5 Timer x Channel Value Registers (TPMxCnVH:TPMxCnVL) ....................................174 10.5 Functional Description ..................................................................................................................175 10.5.1 Counter ..........................
Section Number Title Page 12.1.3 MISO — Master Data In, Slave Data Out ....................................................................204 12.1.4 SS — Slave Select ........................................................................................................204 12.2 Modes of Operation .......................................................................................................................205 12.2.1 SPI in Stop Modes .............................................................
Section Number Title Page Chapter 14 Analog-to-Digital Converter (S08ADC10V1) 14.1 Overview .......................................................................................................................................233 14.2 Channel Assignments ....................................................................................................................233 14.2.1 Alternate Clock .............................................................................................................
Section Number Title Page Chapter 15 Development Support 15.1 Introduction ...................................................................................................................................261 15.1.1 Features .........................................................................................................................262 15.2 Background Debug Controller (BDC) ..........................................................................................262 15.2.
Section Number Title Page Appendix B Ordering Information and Mechanical Drawings B.1 Ordering Information .....................................................................................................................309 B.2 Orderable Part Numbering System ................................................................................................310 B.2.1 Consumer and Industrial Orderable Part Numbering System .......................................310 B.2.
Chapter 1 Introduction 1.1 Overview The MC9S08AW60, MC9S08AW48, MC9S08AW32, and MC9S08AW16 are members of the low-cost, high-performance HCS08 family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available with a variety of modules, memory sizes, memory types, and package types. Refer to Table 1-1 for memory sizes and package types. Table 1-2 summarizes the peripheral availability per package type for the devices available in the MC9S08AW60 Series.
HCS08 CORE BDC DEBUG MODULE (DBG) RTI COP IRQ LVD SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) IIC MODULE (IIC1) 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC1) TxD2 SDA1 SCL1 LOW-POWER OSCILLATOR SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) VOLTAGE REGULATOR 2-CHANNEL TIMER/PWM MODULE (TPM2) PTE7/SPSCK1 MISO1 SS1 TPM1CLK TPM1CH5– TPM1CH0 RxD1 TxD1 PORT E INTERNAL CLOCK GENERATOR (ICG) 6-CHANNEL TIMER/PWM MODULE (TPM1) SPSCK1 MOSI1 6 TPM2CLK PORT F USER RAM AW60/48/32 = 2048 BYTES AW16 =
Chapter 1 Introduction Table 1-3 lists the functional versions of the on-chip modules. Table 1-3. Versions of On-Chip Modules Module Analog-to-Digital Converter Version (S08ADC10) 1 (S08ICG) 4 (S08IIC) 1 Keyboard Interrupt (S08KBI) 1 Serial Communications Interface (S08SCI) 2 Serial Peripheral Interface (S08SPI) 3 Timer Pulse-Width Modulator (S08TPM) 2 Central Processing Unit (S08CPU) 2 (DBG) 2 Internal Clock Generator Inter-Integrated Circuit Debug Module 1.
Chapter 1 Introduction • • • — The output of the digitally-controlled oscillator (DCO) in the frequency-locked loop sub-module — Control bits inside the ICG determine which source is connected. FFE is a control signal generated inside the ICG. If the frequency of ICGOUT > 4 × the frequency of ICGERCLK, this signal is a logic 1 and the fixed-frequency clock will be ICGERCLK/2. Otherwise the fixed-frequency clock will be BUSCLK.
Chapter 2 Pins and Connections 2.1 Introduction This chapter describes signals that connect to package pins. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals.
Chapter 2 Pins and Connections PTC2/MCLK PTC1/SDA1 PTC0/SCL1 VSS PTG6/EXTAL PTG5/XTAL BKGD/MS VREFL VREFH PTD7/KBI1P7/AD1P15 PTD6/TPM1CLK/AD1P14 PTD5/AD1P13 PTD4/TPM2CLK/AD1P12 63 62 61 60 59 58 57 56 55 54 53 52 51 50 64 PTC4 1 PTG4/KBI1P4 PTC3/TxD2 Device Pin Assignment PTC5/RxD2 2.
VREFH PTG4/KB1IP4 38 37 39 VREFL 40 BKGD/MS 41 PTG5/XTAL 42 PTG6/EXTAL 43 VSS 44 PTC0/SCL1 45 PTC1/SDA1 46 PTC2/MCLK 47 PTC3/TxD2 48 PTC5/RxD2 Chapter 2 Pins and Connections PTC4 1 36 PTG3/KBI1P3 IRQ 2 35 PTD3/KBI1P6/AD1P11 RESET 3 34 PTD2/KBI1P5/AD1P10 PTF0/TPM1CH2 4 33 VSSAD PTF1/TPM1CH3 5 32 VDDAD PTF4/TPM2CH0 6 31 PTD1/AD1P9 48-Pin QFN PTA2 24 25 PTA7 PTA1 23 PTE3/TPM1CH1 12 PTA0 22 26 PTB0/AD1P0 PTG2/KBI1P2 21 PTE2/TPM1CH0 11 PTG1/KBI1P1 20 27 PTB1/AD1P1 PTG0/KBI1P0 19
34 44 43 PTC4 1 VREFH VREFL BKGD/MS PTG5/XTAL PTG6/EXTAL VSS PTC0/SCL1 PTC1/SDA1 PTC2/MCLK PTC3/TxD2 PTC5/RxD2 Chapter 2 Pins and Connections 42 41 40 39 38 37 36 35 33 PTG3/KBI1P3 IRQ 2 32 PTD3/KBI1P6/AD1P11 RESET 3 31 PTD2/KBI1P5/AD1P10 PTF0/TPM1CH2 4 30 VSSAD PTF1/TPM1CH3 5 29 VDDAD 28 PTD1/AD1P9 44-Pin LQFP PTF4/TPM2CH0 6 PTF5/TPM2CH1 7 27 PTD0/AD1P8 PTE0/TxD1 8 26 PTB3/AD1P3 PTE1/RxD1 9 25 PTB2/AD1P2 PTE2/TPM1CH0 10 24 PTB1/AD1P1 PTE3/TPM1CH1
Chapter 2 Pins and Connections VREFH CBYAD 0.1 μF PTA0 + CBLK + 10 μF 5V PTA1 VSSAD VREFL VDD VDD SYSTEM POWER MC9S08AW60 VDDAD PTA2 PORT A CBY 0.1 μF PTA3 PTA4 PTA5 VSS (x2) PTA6 PTA7 NOTE 1 RF C1 PTB0/AD1P0 RS XTAL NOTE 2 C2 X1 EXTAL NOTE 2 PTB1/AD1P1 PTB2/AD1P2 PORT B 1 BKGD/MS VDD 4.7 kΩ–10 kΩ PORT C INTERRUPT INPUT 0.1 μF I/O AND PTB7/AD1P7 PERIPHERAL PTC0/SCL1 INTERFACE TO PTC1/SDA1 APPLICATION PTC3/TxD2 SYSTEM PTC4 PTC5/RxD2 4.
Chapter 2 Pins and Connections 2.3.1 Power (VDD, 2 x VSS, VDDAD, VSSAD) VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides regulated lower-voltage source to the CPU and other internal circuitry of the MCU. Typically, application systems have two separate capacitors across the power pins.
Chapter 2 Pins and Connections 2.3.3 RESET Pin RESET is a dedicated pin with a pullup device built in. It has input hysteresis, a high current output driver, and no output slew rate control. Internal power-on reset and low-voltage reset circuitry typically make external reset circuitry unnecessary. This pin is normally connected to the standard 6-pin background debug connector so a development system can directly reset the MCU system.
Chapter 2 Pins and Connections When IRQ is configured as the IRQ input and is set to detect rising edges, a pulldown device rather than a pullup device is enabled. In EMC-sensitive applications, an external RC filter is recommended on the IRQ pin. See Figure 2-4 for an example. 2.3.7 General-Purpose I/O and Peripheral Ports The remaining pins are shared among general-purpose I/O and on-chip peripheral functions such as timers and serial I/O systems.
Chapter 2 Pins and Connections Table 2-1. Pin Sharing Priority Lowest <- Pin Function Priority -> Highest Port Pins 1 Alternate Function Reference1 Alternate Function PTF3–PTF0 TPM1CH5– TPM1CH2 Chapter 10, “Timer/PWM (S08TPMV2)” PTG4–PTG0 KBI1P4–KBI1P0 Chapter 9, “Keyboard Interrupt (S08KBIV1)” PTG6–PTG5 EXTAL–XTAL Chapter 8, “Internal Clock Generator (S08ICGV4)” See the listed chapter for information about modules that share these pins.
Chapter 2 Pins and Connections MC9S08AW60 Data Sheet, Rev 2 32 Freescale Semiconductor
Chapter 3 Modes of Operation 3.1 Introduction The operating modes of the MC9S08AW60 Series are described in this chapter. Entry into each mode, exit from each mode, and functionality while in each of the modes are described. 3.2 • • • 3.
Chapter 3 Modes of Operation After entering active background mode, the CPU is held in a suspended state waiting for serial background commands rather than executing instructions from the user’s application program. Background commands are of two types: • Non-intrusive commands, defined as commands that can be issued while the user program is running.
Chapter 3 Modes of Operation the CPU executes a STOP instruction, the MCU will not enter either of the stop modes and an illegal opcode reset is forced. The stop modes are selected by setting the appropriate bits in SPMSC2. HCS08 devices that are designed for low voltage operation (1.8V to 3.6V) also include stop1 mode. The MC9S08AW60 Series family of devices does not include stop1 mode. Table 3-1 summarizes the behavior of the MCU in each of the stop modes. Table 3-1.
Chapter 3 Modes of Operation After waking up from stop2, the PPDF bit in SPMSC2 is set. This flag may be used to direct user code to go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched until a logic 1 is written to PPDACK in SPMSC2. To maintain I/O state for pins that were configured as general-purpose I/O, the user must restore the contents of the I/O port registers, which have been saved in RAM, to the port registers before writing to the PPDACK bit.
Chapter 3 Modes of Operation Table 3-2. BDM Enabled Stop Mode Behavior Mode PPDC CPU, Digital Peripherals, FLASH RAM ICG ADC1 Regulator I/O Pins RTI Stop3 0 Standby Standby Active Optionally on Active States held Optionally on 3.6.4 LVD Enabled in Stop Mode The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below the LVD voltage.
Chapter 3 Modes of Operation Table 3-4. Stop Mode Behavior (continued) Mode Peripheral Stop2 Stop3 KBI Off Optionally On3 RTI Optionally On4 Optionally On4 SCI Off Standby SPI Off Standby TPM Off Standby Standby Standby States Held States Held Voltage Regulator I/O Pins 1 Requires the asynchronous ADC clock and LVD to be enabled, else in standby. 2 OSCSTEN set in ICSC1, else in standby. For high frequency range (RANGE in ICSC2 set) requires the LVD to also be enabled in stop3.
Chapter 4 Memory 4.1 MC9S08AW60 Series Memory Map Figure 4-1 shows the memory map for the MC9S08AW60 and MC9S08AW48 MCUs. Figure 4-2 shows the memory map for the MC9S08AW32 and MC9S08AW16 MCUs. On-chip memory in the MC9S08AW60 Series of MCUs consists of RAM, FLASH program memory for nonvolatile data storage, plus I/O and control/status registers.
Chapter 4 Memory $0000 $006F $0070 DIRECT PAGE REGISTERS $0000 DIRECT PAGE REGISTERS $006F $0070 RAM RAM 2048 BYTES $086F $0870 $17FF $1800 2048 BYTES $086F $0870 FLASH RESERVED 3984 BYTES 3984 BYTES $17FF $1800 HIGH PAGE REGISTERS $185F $1860 HIGH PAGE REGISTERS $185F $1860 RESERVED 10,144 BYTES $3FFF $4000 FLASH 59,296 BYTES FLASH 49,152 BYTES $FFFF $FFFF MC9S08AW60 MC9S08AW48 Figure 4-1.
Chapter 4 Memory $0000 $006F $0070 DIRECT PAGE REGISTERS DIRECT PAGE REGISTERS $006F $0070 RAM RAM 1024 BYTES $046F $0470 2048 BYTES $086F $0870 $0000 RESERVED RESERVED 5008 BYTES 3984 BYTES $17FF $1800 $17FF $1800 HIGH PAGE REGISTERS HIGH PAGE REGISTERS $185F $1860 $185F $1860 RESERVED RESERVED 26,528 BYTES 42,912 BYTES $7FFF $8000 $BFFF $C000 FLASH FLASH 32,768 BYTES 16,384 BYTES $FFFF $FFFF MC9S08AW32 MC9S08AW16 Figure 4-2.
Chapter 4 Memory 4.1.1 Reset and Interrupt Vector Assignments Figure 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the Freescale-provided equate file for the MC9S08AW60 Series. For more details about resets, interrupts, interrupt priority, and local interrupt mask controls, refer to Chapter 5, “Resets, Interrupts, and System Configuration.” Table 4-1.
Chapter 4 Memory 4.2 Register Addresses and Bit Assignments The registers in the MC9S08AW60 Series are divided into these three groups: • Direct-page registers are located in the first 112 locations in the memory map, so they are accessible with efficient direct addressing mode instructions. • High-page registers are used much less often, so they are located above $1800 in the memory map. This leaves more room in the direct page for more frequently used registers and variables.
Chapter 4 Memory Table 4-2.
Chapter 4 Memory Table 4-2.
Chapter 4 Memory Table 4-2.
Chapter 4 Memory High-page registers, shown in Table 4-3, are accessed much less often than other I/O and control registers so they have been located outside the direct addressable memory space, starting at $1800. Table 4-3.
Chapter 4 Memory Table 4-3.
Chapter 4 Memory Table 4-4.
Chapter 4 Memory When security is enabled, the RAM is considered a secure memory resource and is not accessible through BDM or through code executing from non-secure memory. See Section 4.5, “Security” for a detailed description of the security feature. 4.4 FLASH The FLASH memory is intended primarily for program storage. In-circuit programming allows the operating program to be loaded into the FLASH memory after final assembly of the application product.
Chapter 4 Memory 4.4.
Chapter 4 Memory 4.4.3 Program and Erase Command Execution The steps for executing any of the commands are listed below. The FCDIV register must be initialized and any error flags cleared before beginning command execution. The command execution steps are: 1. Write a data value to an address in the FLASH array. The address and data information from this write is latched into the FLASH interface. This write is a required first step in any command sequence.
Chapter 4 Memory WRITE TO FCDIV (Note 1) FLASH PROGRAM AND ERASE FLOW Note 1: Required only once after reset. START FACCERR ? 0 1 CLEAR ERROR WRITE TO FLASH TO BUFFER ADDRESS AND DATA WRITE COMMAND TO FCMD WRITE 1 TO FCBEF TO LAUNCH COMMAND AND CLEAR FCBEF (Note 2) FPVIOL OR FACCERR ? Note 2: Wait at least four bus cycles before checking FCBEF or FCCF. YES ERROR EXIT NO 0 FCCF ? 1 DONE Figure 4-3. FLASH Program and Erase Flowchart 4.4.
Chapter 4 Memory The first byte of a series of sequential bytes being programmed in burst mode will take the same amount of time to program as a byte programmed in standard mode. Subsequent bytes will program in the burst program time provided that the conditions above are met. In the case the next sequential address is the beginning of a new row, the program time for that byte will be the standard time instead of the burst time.
Chapter 4 Memory 4.4.5 Access Errors An access error occurs whenever the command execution protocol is violated. Any of the following specific actions will cause the access error flag (FACCERR) in FSTAT to be set. FACCERR must be cleared by writing a 1 to FACCERR in FSTAT before any command can be processed.
Chapter 4 Memory be programmed to logic 0 to enable block protection. Therefore the value $DE must be programmed into NVPROT to protect addresses $E000 through $FFFF. FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1 A15 A14 A13 A12 A11 A10 A9 1 1 1 1 1 1 1 1 1 A8 A7 A6 A5 A4 A3 A2 A1 A0 Figure 4-5. Block Protection Mechanism One use for block protection is to block protect an area of FLASH memory for a bootloader program.
Chapter 4 Memory the MCU secure. During development, whenever the FLASH is erased, it is good practice to immediately program the SEC00 bit to 0 in NVOPT so SEC01:SEC00 = 1:0. This would allow the MCU to remain unsecured after a subsequent reset. The on-chip debug module cannot be enabled while the MCU is secure.
Chapter 4 Memory 4.6 FLASH Registers and Control Bits The FLASH module has nine 8-bit registers in the high-page register space, three locations in the nonvolatile register space in FLASH memory which are copied into three corresponding high-page control registers at reset. There is also an 8-byte comparison key in FLASH memory. Refer to Table 4-3 and Table 4-4 for the absolute address assignments for all FLASH registers. This section refers to registers and control bits only by their names.
Chapter 4 Memory Table 4-7. FLASH Clock Divider Settings fBus PRDIV8 (Binary) DIV5:DIV0 (Decimal) fFCLK Program/Erase Timing Pulse (5 μs Min, 6.7 μs Max) 20 MHz 1 12 192.3 kHz 5.2 μs 10 MHz 0 49 200 kHz 5 μs 8 MHz 0 39 200 kHz 5 μs 4 MHz 0 19 200 kHz 5 μs 2 MHz 0 9 200 kHz 5 μs 1 MHz 0 4 200 kHz 5 μs 200 kHz 0 0 200 kHz 5 μs 150 kHz 0 0 150 kHz 6.7 μs 4.6.
Chapter 4 Memory Table 4-9. Security States SEC01:SEC00 Description 0:0 secure 0:1 secure 1:0 unsecured 1:1 secure SEC01:SEC00 changes to 1:0 after successful backdoor key entry or a successful blank check of FLASH. 4.6.3 FLASH Configuration Register (FCNFG) Bits 7 through 5 may be read or written at any time. Bits 4 through 0 always read 0 and cannot be written. R 7 6 0 0 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 KEYACC W Reset 0 0 0 = Unimplemented or Reserved Figure 4-8.
Chapter 4 Memory 4.6.4 FLASH Protection Register (FPROT and NVPROT) During reset, the contents of the nonvolatile location NVPROT are copied from FLASH into FPROT. This register may be read at any time. • If FPDIS = 0, then protection can be increased (in other words, a smaller value of FPS can be written). • If FPDIS = 1, then writes do not change protection.
Chapter 4 Memory Table 4-12. FSTAT Register Field Descriptions Field Description 7 FCBEF FLASH Command Buffer Empty Flag — The FCBEF bit is used to launch commands. It also indicates that the command buffer is empty so that a new command sequence can be executed when performing burst programming. The FCBEF bit is cleared by writing a one to it or when a burst program command is transferred to the array for programming. Only burst program commands can be buffered.
Chapter 4 Memory 4.6.6 FLASH Command Register (FCMD) Only five command codes are recognized in normal user modes as shown in Table 4-14. Refer to Section 4.4.3, “Program and Erase Command Execution” for a detailed discussion of FLASH programming and erase operations. 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W FCMD7 FCMD6 FCMD5 FCMD4 FCMD3 FCMD2 FCMD1 FCMD0 0 0 0 0 0 0 0 0 Reset Figure 4-11. FLASH Command Register (FCMD) Table 4-13.
Chapter 4 Memory MC9S08AW60 Data Sheet, Rev 2 64 Freescale Semiconductor
Chapter 5 Resets, Interrupts, and System Configuration 5.1 Introduction This chapter discusses basic reset and interrupt mechanisms and the various sources of reset and interrupts in the MC9S08AW60 Series. Some interrupt sources from peripheral modules are discussed in greater detail within other chapters of this data manual. This chapter gathers basic information about all reset and interrupt sources in one place for easy reference.
Chapter 5 Resets, Interrupts, and System Configuration • • • • Illegal opcode detect Background debug forced reset The reset pin (RESET) Clock generator loss of lock and loss of clock reset Each of these sources, with the exception of the background debug forced reset, has an associated bit in the system reset status register. Whenever the MCU enters reset, the internal clock generator (ICG) module switches to self-clocked mode with the frequency of fSelf_reset selected.
Chapter 5 Resets, Interrupts, and System Configuration I bit in the CCR is 0 to allow interrupts. The global interrupt mask (I bit) in the CCR is initially set after reset which masks (prevents) all maskable interrupt sources. The user program initializes the stack pointer and performs other system setup before clearing the I bit to allow the CPU to respond to interrupts. When the CPU receives a qualified interrupt request, it completes the current instruction before responding to the interrupt.
Chapter 5 Resets, Interrupts, and System Configuration TOWARD LOWER ADDRESSES UNSTACKING ORDER 7 0 SP AFTER INTERRUPT STACKING 5 1 CONDITION CODE REGISTER 4 2 ACCUMULATOR 3 3 INDEX REGISTER (LOW BYTE X)* 2 4 PROGRAM COUNTER HIGH 1 5 PROGRAM COUNTER LOW STACKING ORDER SP BEFORE THE INTERRUPT TOWARD HIGHER ADDRESSES * High byte (H) of index register is not automatically stacked. Figure 5-1.
Chapter 5 Resets, Interrupts, and System Configuration NOTE The voltage measured on the pulled up IRQ pin may be as low as VDD – 0.7 V. The internal gates connected to this pin are pulled all the way to VDD. All other pins with enabled pullup resistors will have an unloaded measurement of VDD. 5.5.2.2 Edge and Level Sensitivity The IRQMOD control bit reconfigures the detection logic so it detects edge events and pin levels.
Chapter 5 Resets, Interrupts, and System Configuration Table 5-1.
Chapter 5 Resets, Interrupts, and System Configuration 5.6 Low-Voltage Detect (LVD) System The MC9S08AW60 Series includes a system to protect against low voltage conditions in order to protect memory contents and control MCU system states during supply voltage variations. The system is comprised of a power-on reset (POR) circuit and an LVD circuit with a user selectable trip voltage, either high (VLVDH) or low (VLVDL).
Chapter 5 Resets, Interrupts, and System Configuration Either RTI clock source can be used when the MCU is in run, wait or stop3 mode. When using the external oscillator in stop3, it must be enabled in stop (OSCSTEN = 1) and configured for low bandwidth operation (RANGE = 0). Only the internal 1-kHz clock source can be selected to wake the MCU from stop2 mode.
Chapter 5 Resets, Interrupts, and System Configuration 5.9.1 Interrupt Pin Request Status and Control Register (IRQSC) This direct page register includes two unimplemented bits which always read 0, four read/write bits, one read-only status bit, and one write-only bit. These bits are used to configure the IRQ function, report status, and acknowledge IRQ events.
Chapter 5 Resets, Interrupts, and System Configuration 5.9.2 System Reset Status Register (SRS) This register includes seven read-only status flags to indicate the source of the most recent reset. When a debug host forces reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS will be set. Writing any value to this register address clears the COP watchdog timer without affecting the contents of this register. The reset state of these bits depends on what caused the MCU to reset.
Chapter 5 Resets, Interrupts, and System Configuration Table 5-3. SRS Register Field Descriptions (continued) Field Description 2 ICG Internal Clock Generation Module Reset — Reset was caused by an ICG module reset. 0 Reset not caused by ICG module. 1 Reset caused by ICG module. 1 LVD Low Voltage Detect — If the LVDRE and LVDSE bits are set and the supply drops below the LVD trip voltage, an LVD reset will occur. This bit is also set by POR. 0 Reset not caused by LVD trip or POR.
Chapter 5 Resets, Interrupts, and System Configuration 7 6 5 COPE COPT STOPE 1 1 0 4 R 3 2 0 0 0 0 1 0 1 1 W Reset 1 = Unimplemented or Reserved Figure 5-5. System Options Register (SOPT) Table 5-5. SOPT Register Field Descriptions Field Description 7 COPE COP Watchdog Enable — This write-once bit defaults to 1 after reset. 0 COP watchdog timer disabled. 1 COP watchdog timer enabled (force reset on timeout).
Chapter 5 Resets, Interrupts, and System Configuration 5.9.6 System Device Identification Register (SDIDH, SDIDL) This read-only register is included so host development systems can identify the HCS08 derivative. This allows the development software to recognize where specific memory blocks, registers, and control bits are located in a target MCU. 7 6 5 4 R 3 2 1 0 ID11 ID10 ID9 ID8 0 0 0 0 W Reset — — — — = Unimplemented or Reserved Figure 5-7.
Chapter 5 Resets, Interrupts, and System Configuration 5.9.7 System Real-Time Interrupt Status and Control Register (SRTISC) This register contains one read-only status flag, one write-only acknowledge bit, three read/write delay selects, and three unimplemented bits, which always read 0. R 7 6 RTIF 0 W 5 4 RTICLKS RTIE 0 0 3 2 1 0 RTIS2 RTIS1 RTIS0 0 0 0 0 RTIACK Reset 0 0 0 = Unimplemented or Reserved Figure 5-9. System RTI Status and Control Register (SRTISC) Table 5-9.
Chapter 5 Resets, Interrupts, and System Configuration 5.9.8 R System Power Management Status and Control 1 Register (SPMSC1) 7 6 LVDF 0 W Reset 5 4 3 2 LVDIE LVDRE(2) LVDSE(2) LVDE(2) 0 1 1 1 1 1 0 BGBE LVDACK 0 0 0 0 = Unimplemented or Reserved 1 2 Bit 1 is a reserved bit that must always be written to 0. This bit can be written only one time after reset. Additional writes are ignored. Figure 5-10. System Power Management Status and Control 1 Register (SPMSC1) Table 5-11.
Chapter 5 Resets, Interrupts, and System Configuration 5.9.9 System Power Management Status and Control 2 Register (SPMSC2) This register is used to report the status of the low voltage warning function, and to configure the stop mode behavior of the MCU.
Chapter 6 Parallel Input/Output 6.1 Introduction This chapter explains software controls related to parallel input/output (I/O). The MC9S08AW60 has seven I/O ports which include a total of 54 general-purpose I/O pins. See Chapter 2, “Pins and Connections” for more information about the logic and hardware aspects of these pins. Many of these pins are shared with on-chip peripherals such as timer systems, communication systems, or keyboard interrupts.
Chapter 6 Parallel Input/Output • • • • • • • • Software-controlled slew rate output buffers Eight port A pins Eight port B pins shared with ADC1 Seven port C pins shared with SCI2, IIC1, and MCLK Eight port D pins shared with ADC1, KBI1, and TPM1 and TPM2 external clock inputs Eight port E pins shared with SCI1, TPM1, and SPI1 Eight port F pins shared with TPM1 and TPM2 Seven port G pins shared with XTAL, EXTAL, and KBI1 6.
Chapter 6 Parallel Input/Output Port B pins are general-purpose I/O pins. Parallel I/O function is controlled by the port B data (PTBD) and data direction (PTBDD) registers which are located in page zero register space. The pin control registers, pullup enable (PTBPE), slew rate control (PTBSE), and drive strength select (PTBDS) are located in the high page registers. Refer to Section 6.4, “Parallel I/O Control” for more information about general-purpose I/O control and Section 6.
Chapter 6 Parallel Input/Output pullup enable (PTDPE), slew rate control (PTDSE), and drive strength select (PTDDS) are located in the high page registers. Refer to Section 6.4, “Parallel I/O Control” for more information about general-purpose I/O control and Section 6.5, “Pin Control” for more information about pin control. Port D general-purpose I/O are shared with the ADC, KBI, and TPM1 and TPM2 external clock inputs.
Chapter 6 Parallel Input/Output 6.3.6 Port F Port F MCU Pin: Bit 7 6 5 PTF7 PTF6 4 3 2 1 Bit 0 PTF5/ PTF4/ PTF3/ PTF2/ PTF1/ PTF0/ TPM2CH1 TPM2CH0 TPM1CH5 TPM1CH4 TPM1CH3 TPM1CH2 Figure 6-6. Port F Pin Names Port F pins are general-purpose I/O pins. Parallel I/O function is controlled by the port F data (PTFD) and data direction (PTFDD) registers which are located in page zero register space.
Chapter 6 Parallel Input/Output 6.4 Parallel I/O Control Reading and writing of parallel I/O is done through the port data registers. The direction, input or output, is controlled through the port data direction registers. The parallel I/O port function for an individual pin is illustrated in the block diagram below. PTxDDn D Output Enable Q PTxDn D Output Data Q 1 Port Read Data 0 Synchronizer Input Data BUSCLK Figure 6-8.
Chapter 6 Parallel Input/Output 6.5 Pin Control The pin control registers are located in the high page register block of the memory. These registers are used to control pullups, slew rate, and drive strength for the I/O pins. The pin control registers operate independently of the parallel I/O registers. 6.5.1 Internal Pullup Enable An internal pullup device can be enabled for each port pin by setting the corresponding bit in one of the pullup enable registers (PTxPEn).
Chapter 6 Parallel Input/Output 6.6 Pin Behavior in Stop Modes Depending on the stop mode, I/O functions differently as the result of executing a STOP instruction. An explanation of I/O behavior for the various stop modes follows: • Stop2 mode is a partial power-down mode, whereby I/O latches are maintained in their state as before the STOP instruction was executed.
Chapter 6 Parallel Input/Output 7 6 5 4 3 2 1 0 PTADD7 PTADD6 PTADD5 PTADD4 PTADD3 PTADD2 PTADD1 PTADD0 0 0 0 0 0 0 0 0 R W Reset Figure 6-10. Data Direction for Port A Register (PTADD) Table 6-3. PTADD Register Field Descriptions Field Description 7:0 Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for PTADD[7:0] PTAD reads. 0 Input (output driver disabled) and reads return the pin value.
Chapter 6 Parallel Input/Output 7 6 5 4 3 2 1 0 PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0 0 0 0 0 0 0 0 0 R W Reset Figure 6-12. Output Slew Rate Control Enable for Port A (PTASE) Table 6-5. PTASE Register Field Descriptions Field Description 7:0 Output Slew Rate Control Enable for Port A Bits — Each of these control bits determine whether output slew PTASE[7:0] rate control is enabled for the associated PTA pin.
Chapter 6 Parallel Input/Output 6.7.3 Port B I/O Registers (PTBD and PTBDD) Port B parallel I/O function is controlled by the registers listed below. 7 6 5 4 3 2 1 0 PTBD7 PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD0 0 0 0 0 0 0 0 0 R W Reset Figure 6-14. Port B Data Register (PTBD) Table 6-7. PTBD Register Field Descriptions Field Description 7:0 PTBD[7:0] Port B Data Register Bits — For port B pins that are inputs, reads return the logic level on the pin.
Chapter 6 Parallel Input/Output 6.7.4 Port B Pin Control Registers (PTBPE, PTBSE, PTBDS) In addition to the I/O control, port B pins are controlled by the registers listed below. 7 6 5 4 3 2 1 0 PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0 0 0 0 0 0 0 0 0 R W Reset Figure 6-16. Internal Pullup Enable for Port B (PTBPE) Table 6-9.
Chapter 6 Parallel Input/Output 7 6 5 4 3 2 1 0 PTBDS7 PTBDS6 PTBDS5 PTBDS4 PTBDS3 PTBDS2 PTBDS1 PTBDS0 0 0 0 0 0 0 0 0 R W Reset Figure 6-18. Output Drive Strength Selection for Port B (PTBDS) Table 6-11. PTBDS Register Field Descriptions Field Description 7:0 Output Drive Strength Selection for Port B Bits — Each of these control bits selects between low and high PTBDS[7:0] output drive for the associated PTB pin. 0 Low output drive enabled for port B bit n.
Chapter 6 Parallel Input/Output 6.7.5 Port C I/O Registers (PTCD and PTCDD) Port C parallel I/O function is controlled by the registers listed below. 7 6 5 4 3 2 1 0 PTCD6 PTCD5 PTCD4 PTCD3 PTCD2 PTCD1 PTCD0 0 0 0 0 0 0 0 R W Reset 0 Figure 6-19. Port C Data Register (PTCD) Table 6-12. PTCD Register Field Descriptions Field Description 6:0 PTCD[6:0] Port C Data Register Bits — For port C pins that are inputs, reads return the logic level on the pin.
Chapter 6 Parallel Input/Output 6.7.6 Port C Pin Control Registers (PTCPE, PTCSE, PTCDS) In addition to the I/O control, port C pins are controlled by the registers listed below. 7 6 5 4 3 2 1 0 PTCPE6 PTCPE5 PTCPE4 PTCPE3 PTCPE2 PTCPE1 PTCPE0 0 0 0 0 0 0 0 R W Reset 0 Figure 6-21. Internal Pullup Enable for Port C (PTCPE) Table 6-14.
Chapter 6 Parallel Input/Output 7 6 5 4 3 2 1 0 PTCDS6 PTCDS5 PTCDS4 PTCDS3 PTCDS2 PTCDS1 PTCDS0 0 0 0 0 0 0 0 R W Reset 0 Figure 6-23. Output Drive Strength Selection for Port C (PTCDS) Table 6-16. PTCDS Register Field Descriptions Field Description 6:0 Output Drive Strength Selection for Port C Bits — Each of these control bits selects between low and high PTCDS[6:0] output drive for the associated PTC pin. 0 Low output drive enabled for port C bit n.
Chapter 6 Parallel Input/Output 6.7.7 Port D I/O Registers (PTDD and PTDDD) Port D parallel I/O function is controlled by the registers listed below. 7 6 5 4 3 2 1 0 PTDD7 PTDD6 PTDD5 PTDD4 PTDD3 PTDD2 PTDD1 PTDD0 0 0 0 0 0 0 0 0 R W Reset Figure 6-24. Port D Data Register (PTDD) Table 6-17. PTDD Register Field Descriptions Field Description 7:0 PTDD[7:0] Port D Data Register Bits — For port D pins that are inputs, reads return the logic level on the pin.
Chapter 6 Parallel Input/Output 6.7.8 Port D Pin Control Registers (PTDPE, PTDSE, PTDDS) In addition to the I/O control, port D pins are controlled by the registers listed below. 7 6 5 4 3 2 1 0 PTDPE7 PTDPE6 PTDPE5 PTDPE4 PTDPE3 PTDPE2 PTDPE1 PTDPE0 0 0 0 0 0 0 0 0 R W Reset Figure 6-26. Internal Pullup Enable for Port D (PTDPE) Table 6-19.
Chapter 6 Parallel Input/Output 7 6 5 4 3 2 1 0 PTDDS7 PTDDS6 PTDDS5 PTDDS4 PTDDS3 PTDDS2 PTDDS1 PTDDS0 0 0 0 0 0 0 0 0 R W Reset Figure 6-28. Output Drive Strength Selection for Port D (PTDDS) Table 6-21. PTDDS Register Field Descriptions Field Description 7:0 Output Drive Strength Selection for Port D Bits — Each of these control bits selects between low and high PTDDS[7:0] output drive for the associated PTD pin. 0 Low output drive enabled for port D bit n.
Chapter 6 Parallel Input/Output 6.7.9 Port E I/O Registers (PTED and PTEDD) Port E parallel I/O function is controlled by the registers listed below. 7 6 5 4 3 2 1 0 PTED7 PTED6 PTED5 PTED4 PTED3 PTED2 PTED1 PTED0 0 0 0 0 0 0 0 0 R W Reset Figure 6-29. Port E Data Register (PTED) Table 6-22. PTED Register Field Descriptions Field Description 7:0 PTED[7:0] Port E Data Register Bits — For port E pins that are inputs, reads return the logic level on the pin.
Chapter 6 Parallel Input/Output 6.7.10 Port E Pin Control Registers (PTEPE, PTESE, PTEDS) In addition to the I/O control, port E pins are controlled by the registers listed below. 7 6 5 4 3 2 1 0 PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0 0 0 0 0 0 0 0 0 R W Reset Figure 6-31. Internal Pullup Enable for Port E (PTEPE) Table 6-24.
Chapter 6 Parallel Input/Output 7 6 5 4 3 2 1 0 PTEDS7 PTEDS6 PTEDS5 PTEDS4 PTEDS3 PTEDS2 PTEDS1 PTEDS0 0 0 0 0 0 0 0 0 R W Reset Figure 6-33. Output Drive Strength Selection for Port E (PTEDS) Table 6-26. PTEDS Register Field Descriptions Field Description 7:0 Output Drive Strength Selection for Port E Bits — Each of these control bits selects between low and high PTEDS[7:0] output drive for the associated PTE pin. 0 Low output drive enabled for port E bit n.
Chapter 6 Parallel Input/Output 6.7.11 Port F I/O Registers (PTFD and PTFDD) Port F parallel I/O function is controlled by the registers listed below. 7 6 5 4 3 2 1 0 PTFD7 PTFD6 PTFD5 PTFD4 PTFD3 PTFD2 PTFD1 PTFD0 0 0 0 0 0 0 0 0 R W Reset Figure 6-34. Port F Data Register (PTFD) Table 6-27. PTFD Register Field Descriptions Field Description 7:0 PTFD[7:0] Port F Data Register Bits— For port F pins that are inputs, reads return the logic level on the pin.
Chapter 6 Parallel Input/Output 6.7.12 Port F Pin Control Registers (PTFPE, PTFSE, PTFDS) In addition to the I/O control, port F pins are controlled by the registers listed below. 7 6 5 4 3 2 1 0 PTFPE7 PTFPE6 PTFPE5 PTFPE4 PTFPE3 PTFPE2 PTFPE1 PTFPE0 0 0 0 0 0 0 0 0 R W Reset Figure 6-36. Internal Pullup Enable for Port F (PTFPE) Table 6-29.
Chapter 6 Parallel Input/Output 7 6 5 4 3 2 1 0 PTFDS7 PTFDS6 PTFDS5 PTFDS4 PTFDS3 PTFDS2 PTFDS1 PTFDS0 0 0 0 0 0 0 0 0 R W Reset Figure 6-38. Output Drive Strength Selection for Port F (PTFDS) Table 6-31. PTFDS Register Field Descriptions Field Description 7:0 Output Drive Strength Selection for Port F Bits — Each of these control bits selects between low and high PTFDS[7:0] output drive for the associated PTF pin. 0 Low output drive enabled for port F bit n.
Chapter 6 Parallel Input/Output 6.7.13 Port G I/O Registers (PTGD and PTGDD) Port G parallel I/O function is controlled by the registers listed below. 7 6 5 4 3 2 1 0 PTGD6 PTGD5 PTGD4 PTGD3 PTGD2 PTGD1 PTGD0 0 0 0 0 0 0 0 R W Reset 0 Figure 6-39. Port G Data Register (PTGD) Table 6-32. PTGD Register Field Descriptions Field Description 6:0 PTGD[6:0] Port G Data Register Bits — For port G pins that are inputs, reads return the logic level on the pin.
Chapter 6 Parallel Input/Output 6.7.14 Port G Pin Control Registers (PTGPE, PTGSE, PTGDS) In addition to the I/O control, port G pins are controlled by the registers listed below. 7 6 5 4 3 2 1 0 PTGPE6 PTGPE5 PTGPE4 PTGPE3 PTGPE2 PTGPE1 PTGPE0 0 0 0 0 0 0 0 R W Reset 0 Figure 6-41. Internal Pullup Enable for Port G Bits (PTGPE) Table 6-34.
Chapter 6 Parallel Input/Output 7 6 5 4 3 2 1 0 PTGDS6 PTGDS5 PTGDS4 PTGDS3 PTGDS2 PTGDS1 PTGDS0 0 0 0 0 0 0 0 R W Reset 0 Figure 6-43. Output Drive Strength Selection for Port G (PTGDS) Table 6-36. PTGDS Register Field Descriptions Field Description 6:0 Output Drive Strength Selection for Port G Bits — Each of these control bits selects between low and high PTGDS[6:0] output drive for the associated PTG pin. 0 Low output drive enabled for port G bit n.
Chapter 7 Central Processor Unit (S08CPUV2) 7.1 Introduction This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU.
Chapter 7 Central Processor Unit (S08CPUV2) 7.2 Programmer’s Model and CPU Registers Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map. 7 0 ACCUMULATOR A 16-BIT INDEX REGISTER H:X H INDEX REGISTER (HIGH) 8 15 INDEX REGISTER (LOW) 7 X 0 SP STACK POINTER 0 15 PROGRAM COUNTER 7 0 CONDITION CODE REGISTER V 1 1 H I N Z C PC CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-1. CPU Registers 7.2.
Chapter 7 Central Processor Unit (S08CPUV2) 7.2.3 Stack Pointer (SP) This 16-bit address pointer register points at the next available location on the automatic last-in-first-out (LIFO) stack. The stack may be located anywhere in the 64-Kbyte address space that has RAM and can be any size up to the amount of available RAM. The stack is used to automatically save the return address for subroutine calls, the return address and CPU registers during interrupts, and for local variables.
Chapter 7 Central Processor Unit (S08CPUV2) 7 0 CONDITION CODE REGISTER V 1 1 H I N Z C CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-2. Condition Code Register Table 7-1. CCR Register Field Descriptions Field Description 7 V Two’s Complement Overflow Flag — The CPU sets the overflow flag when a two’s complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag.
Chapter 7 Central Processor Unit (S08CPUV2) 7.3 Addressing Modes Addressing modes define the way the CPU accesses operands and data. In the HCS08, all memory, status and control registers, and input/output (I/O) ports share a single 64-Kbyte linear address space so a 16-bit binary address can uniquely identify any memory location. This arrangement means that the same instructions that access variables in RAM can also be used to access I/O and control registers or nonvolatile program space.
Chapter 7 Central Processor Unit (S08CPUV2) 7.3.5 Extended Addressing Mode (EXT) In extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of program memory after the opcode (high byte first). 7.3.6 Indexed Addressing Mode Indexed addressing mode has seven variations including five that use the 16-bit H:X index register pair and two that use the stack pointer as the base reference. 7.3.6.
Chapter 7 Central Processor Unit (S08CPUV2) 7.3.6.7 SP-Relative, 16-Bit Offset (SP2) This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. 7.4 Special Operations The CPU performs a few special operations that are similar to instructions but do not have opcodes like other CPU instructions.
Chapter 7 Central Processor Unit (S08CPUV2) interrupt service routine, this would allow nesting of interrupts (which is not recommended because it leads to programs that are difficult to debug and maintain). For compatibility with the earlier M68HC05 MCUs, the high-order half of the H:X index register pair (H) is not saved on the stack as part of the interrupt sequence.
Chapter 7 Central Processor Unit (S08CPUV2) 7.4.5 BGND Instruction The BGND instruction is new to the HCS08 compared to the M68HC08. BGND would not be used in normal user programs because it forces the CPU to stop processing user instructions and enter the active background mode. The only way to resume execution of the user program is through reset or by a host debug system issuing a GO, TRACE1, or TAGGO serial command through the background debug interface.
Chapter 7 Central Processor Unit (S08CPUV2) 7.5 HCS08 Instruction Set Summary Instruction Set Summary Nomenclature The nomenclature listed here is used in the instruction descriptions in Table 7-2.
Chapter 7 Central Processor Unit (S08CPUV2) 0 1 U = = = = Bit forced to 0 Bit forced to 1 Bit set or cleared according to results of operation Undefined after the operation Machine coding notation dd = Low-order 8 bits of a direct address 0x0000–0x00FF (high byte assumed to be 0x00) ee = Upper 8 bits of 16-bit offset ff = Lower 8 bits of 16-bit offset or 8-bit offset ii = One byte of immediate data jj = High-order byte of a 16-bit immediate data value kk = Low-order byte of a 16-bit immediate data value
Chapter 7 Central Processor Unit (S08CPUV2) IX IX+ IX1 IX1+ = = = = IX2 REL SP1 SP2 = = = = 16-bit indexed no offset 16-bit indexed no offset, post increment (CBEQ and MOV only) 16-bit indexed with 8-bit offset from H:X 16-bit indexed with 8-bit offset, post increment (CBEQ only) 16-bit indexed with 16-bit offset from H:X 8-bit relative offset Stack pointer with 8-bit offset Stack pointer with 16-bit offset Description V H I N Z C ADC ADC ADC ADC ADC ADC ADC ADC ADD ADD ADD ADD ADD ADD ADD ADD #opr8
Chapter 7 Central Processor Unit (S08CPUV2) V H I N Z C DIR (b0) DIR (b1) DIR (b2) (b3) – – – – – – DIR DIR (b4) DIR (b5) DIR (b6) DIR (b7) 11 13 15 17 19 1B 1D 1F dd dd dd dd dd dd dd dd Bus Cycles1 Description Operand Operation Opcode Effect on CCR Source Form Address Mode Table 7-2.
Chapter 7 Central Processor Unit (S08CPUV2) V H I N Z C BRCLR n,opr8a,rel Branch if Bit n in Memory Clear Branch if (Mn) = 0 DIR (b0) DIR (b1) DIR (b2) (b3) – – – – – ↕ DIR DIR (b4) DIR (b5) DIR (b6) DIR (b7) BRN rel Branch Never Uses 3 Bus Cycles – – – – – – REL 21 rr Branch if (Mn) = 1 DIR (b0) DIR (b1) DIR (b2) (b3) – – – – – ↕ DIR DIR (b4) DIR (b5) DIR (b6) DIR (b7) 00 02 04 06 08 0A 0C 0E dd dd dd dd dd dd dd dd Mn ← 1 DIR (b0) DIR (b1) DIR (b2) (b3) – – – – – – DIR DIR (b4) DIR (b5) DI
Chapter 7 Central Processor Unit (S08CPUV2) V H I N Z C CPX CPX CPX CPX CPX CPX CPX CPX #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP DAA DBNZ opr8a,rel DBNZA rel DBNZX rel DBNZ oprx8,X,rel DBNZ ,X,rel DBNZ oprx8,SP,rel DEC opr8a DECA DECX DEC oprx8,X DEC ,X DEC oprx8,SP DIV EOR #opr8i EOR opr8a EOR opr16a EOR oprx16,X EOR oprx8,X EOR ,X EOR oprx16,SP EOR oprx8,SP INC opr8a INCA INCX INC oprx8,X INC ,X INC oprx8,SP JMP opr8a JMP opr16a JMP oprx16,X JMP oprx8,X JMP ,X JSR opr8a JSR opr16a JSR
Chapter 7 Central Processor Unit (S08CPUV2) V H I N Z C LDX #opr8i LDX opr8a LDX opr16a LDX oprx16,X LDX oprx8,X LDX ,X LDX oprx16,SP LDX oprx8,SP LSL opr8a LSLA LSLX LSL oprx8,X LSL ,X LSL oprx8,SP LSR opr8a LSRA LSRX LSR oprx8,X LSR ,X LSR oprx8,SP Load X (Index Register Low) from Memory Logical Shift Left (Same as ASL) Logical Shift Right X ← (M) 0 – – ↕ C 0 b7 0 C b7 b0 (M)destination ← (M)source MOV opr8a,opr8a MOV opr8a,X+ MOV #opr8i,opr8a MOV ,X+,opr8a Move MUL Unsigned multiply ↕ –
Chapter 7 Central Processor Unit (S08CPUV2) V H I N Z C ROR opr8a RORA RORX ROR oprx8,X ROR ,X ROR oprx8,SP Rotate Right through Carry RSP Reset Stack Pointer RTI Return from Interrupt RTS Return from Subroutine SBC SBC SBC SBC SBC SBC SBC SBC #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP Subtract with Carry C b7 SP ← 0xFF (High Byte Not Affected) SP ← (SP) + 0x0001; Pull (CCR) SP ← (SP) + 0x0001; Pull (A) SP ← (SP) + 0x0001; Pull (X) SP ← (SP) + 0x0001; Pull (PCH) SP ← (SP) + 0x00
Chapter 7 Central Processor Unit (S08CPUV2) Description V H I N Z C TAP TAX TPA Transfer Accumulator to CCR Transfer Accumulator to X (Index Register Low) Transfer CCR to Accumulator CCR ← (A) ↕ ↕ ↕ ↕ ↕ Bus Cycles1 Operation Operand Effect on CCR Opcode Source Form Address Mode Table 7-2.
Chapter 7 Central Processor Unit (S08CPUV2) Table 7-3.
Chapter 7 Central Processor Unit (S08CPUV2) Table 7-3.
Chapter 8 Internal Clock Generator (S08ICGV4) The internal clock generation (ICG) module is used to generate the system clocks for the MC9S08AW60 Series MCU. The analog supply lines VDDA and VSSA are internally derived from the MCU’s VDD and VSS pins. Electrical parametric data for the ICG may be found in Appendix A, “Electrical Characteristics and Timing Specifications.
HCS08 CORE BDC DEBUG MODULE (DBG) RTI COP IRQ LVD SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) IIC MODULE (IIC1) 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC1) TxD2 SDA1 SCL1 6-CHANNEL TIMER/PWM MODULE (TPM1) INTERNAL CLOCK GENERATOR (ICG) LOW-POWER OSCILLATOR SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) VOLTAGE REGULATOR 2-CHANNEL TIMER/PWM MODULE (TPM2) SPSCK1 MOSI1 PTE7/SPSCK1 MISO1 SS1 TPM1CLK TPM1CH5– TPM1CH0 RxD1 TxD1 PORT E USER RAM AW60/48/32 = 2048 BYTES AW16 = 1024 BYTES PTD7/AD1
Chapter 8 Internal Clock Generator (S08ICGV4) 8.1 Introduction The ICG provides multiple options for clock sources. This offers a user great flexibility when making choices between cost, precision, current draw, and performance. As seen in Figure 8-3, the ICG consists of four functional blocks. Each of these is briefly described here and then in more detail in a later section. • Oscillator block — The oscillator block provides means for connecting an external crystal or resonator.
Chapter 8 Internal Clock Generator (S08ICGV4) • • • • • • • 8.1.
Chapter 8 Internal Clock Generator (S08ICGV4) 8.1.3 Block Diagram Figure 8-3 is a top-level diagram that shows the functional organization of the internal clock generation (ICG) module. This section includes a general description and a feature list.
Chapter 8 Internal Clock Generator (S08ICGV4) selected, this pin is not used by the ICG. The oscillator is capable of being configured to provide a higher amplitude output for improved noise immunity. This mode of operation is selected by HGO = 1. 8.2.3 External Clock Connections If an external clock is used, then the pins are connected as shown Figure 8-4. ICG EXTAL XTAL VSS NOT CONNECTED CLOCK INPUT Figure 8-4. External Clock Connections 8.2.
Chapter 8 Internal Clock Generator (S08ICGV4) 8.3 Register Definition Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all ICG registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 8.3.
Chapter 8 Internal Clock Generator (S08ICGV4) Table 8-1. ICGC1 Register Field Descriptions (continued) Field 2 OSCSTEN 1 LOCD Description Enable Oscillator in Off Mode — The OSCSTEN bit controls whether or not the oscillator circuit remains enabled when the ICG enters off mode. This bit has no effect if HGO = 1 and RANGE = 1. 0 Oscillator disabled when ICG is in off mode unless ENABLE is high, CLKS = 10, and REFST = 1. 1 Oscillator enabled when ICG is in off mode, CLKS = 1X and REFST = 1.
Chapter 8 Internal Clock Generator (S08ICGV4) 8.3.2 ICG Control Register 2 (ICGC2) 7 6 5 4 3 2 1 0 R LOLRE MFD LOCRE RFD W Reset 0 0 0 0 0 0 0 0 Figure 8-7. ICG Control Register 2 (ICGC2) Table 8-2. ICGC2 Register Field Descriptions Field Description 7 LOLRE Loss of Lock Reset Enable — The LOLRE bit determines what type of request is made by the ICG following a loss of lock indication. The LOLRE bit only has an effect when LOLS is set.
Chapter 8 Internal Clock Generator (S08ICGV4) 8.3.3 ICG Status Register 1 (ICGS1) 7 R 6 CLKST 5 4 3 2 1 0 REFST LOLS LOCK LOCS ERCS ICGIF W Reset 1 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 8-8. ICG Status Register 1 (ICGS1) Table 8-3. ICGS1 Register Field Descriptions Field Description 7:6 CLKST Clock Mode Status — The CLKST bits indicate the current clock mode.
Chapter 8 Internal Clock Generator (S08ICGV4) 8.3.4 R ICG Status Register 2 (ICGS2) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 DCOS 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 8-9. ICG Status Register 2 (ICGS2) Table 8-4.
Chapter 8 Internal Clock Generator (S08ICGV4) 7 6 5 4 3 2 1 0 0 0 0 0 R FLT W Reset 1 1 0 0 Figure 8-11. ICG Lower Filter Register (ICGFLTL) Table 8-6. ICGFLTL Register Field Descriptions Field Description 7:0 FLT Filter Value — The FLT bits indicate the current filter value, which controls the DCO frequency. The FLT bits are read only except when the CLKS bits are programmed to self-clocked mode (CLKS = 00).
Chapter 8 Internal Clock Generator (S08ICGV4) 8.4.1 Off Mode (Off) Normally when the CPU enters stop mode, the ICG will cease all clock activity and is in the off state. However there are two cases to consider when clock activity continues while the CPU is in stop mode, 8.4.1.1 BDM Active When the BDM is enabled, the ICG continues activity as originally programmed. This allows access to memory and control registers via the BDC controller. 8.4.1.
Chapter 8 Internal Clock Generator (S08ICGV4) entering off mode. If CLKS bits are set to 01 or 11 coming out of the Off state, the ICG enters this mode until ICGDCLK is stable as determined by the DCOS bit. After ICGDCLK is considered stable, the ICG automatically closes the loop by switching to FLL engaged (internal or external) as selected by the CLKS bits.
Chapter 8 Internal Clock Generator (S08ICGV4) 8.4.4 FLL Engaged Internal Unlocked FEI unlocked is a temporary state that is entered when FEI is entered and the count error (Δn) output from the subtractor is greater than the maximum nunlock or less than the minimum nunlock, as required by the lock detector to detect the unlock condition.
Chapter 8 Internal Clock Generator (S08ICGV4) 8.4.7.1 FLL Engaged External Unlocked FEE unlocked is entered when FEE is entered and the count error (Δn) output from the subtractor is greater than the maximum nunlock or less than the minimum nunlock, as required by the lock detector to detect the unlock condition. The ICG will remain in this state while the count error (Δn) is greater than the maximum nlock or less than the minimum nlock, as required by the lock detector to detect the lock condition.
Chapter 8 Internal Clock Generator (S08ICGV4) 8.4.9 FLL Loss-of-Clock Detection The reference clock and the DCO clock are monitored under different conditions (see Table 8-8). Provided the reference frequency is being monitored, ERCS = 1 indicates that the reference clock meets minimum frequency requirements. When the reference and/or DCO clock(s) are being monitored, if either one falls below a certain frequency, fLOR and fLOD, respectively, the LOCS status bit will be set to indicate the error.
Chapter 8 Internal Clock Generator (S08ICGV4) 8.4.10 Clock Mode Requirements A clock mode is requested by writing to CLKS1:CLKS0 and the actual clock mode is indicated by CLKST1:CLKST0. Provided minimum conditions are met, the status shown in CLKST1:CLKST0 should be the same as the requested mode in CLKS1:CLKS0. Table 8-9 shows the relationship between CLKS, CLKST, and ICGOUT. It also shows the conditions for CLKS = CLKST or the reason CLKS ≠ CLKST.
Chapter 8 Internal Clock Generator (S08ICGV4) 8.4.11 Fixed Frequency Clock The ICG provides a fixed frequency clock output, XCLK, for use by on-chip peripherals. This output is equal to the internal bus clock, BUSCLK, in all modes except FEE. In FEE mode, XCLK is equal to ICGERCLK ÷ 2 when the following conditions are met: • (P × N) ÷ R ≥ 4 where P is determined by RANGE (see Table 8-11), N and R are determined by MFD and RFD respectively (see Table 8-12). • LOCK = 1.
Chapter 8 Internal Clock Generator (S08ICGV4) Table 8-10. ICG Configuration Consideration Clock Reference Source = Internal 1 Clock Reference Source = External FLL Engaged FEI 4 MHz < fBus < 20 MHz. Medium power (will be less than FEE if oscillator range = high) Good clock accuracy (After IRG is trimmed) Lowest system cost (no external components required) IRG is on. DCO is on.
Chapter 8 Internal Clock Generator (S08ICGV4) Table 8-12. MFD and RFD Decode Table 101 110 111 8.5.2 14 16 18 101 110 111 ÷32 ÷64 ÷128 Example #1: External Crystal = 32 kHz, Bus Frequency = 4.19 MHz In this example, the FLL will be used (in FEE mode) to multiply the external 32 kHz oscillator up to 8.38 MHz to achieve 4.19 MHz bus frequency.
Chapter 8 Internal Clock Generator (S08ICGV4) Bits 11:0 FLT No need for user initialization ICGTRM = $xx Bits 7:0 TRIM Only need to write when trimming internal oscillator; not used when external crystal is clock source Figure 8-14 shows flow charts for three conditions requiring ICG initialization. RESET INITIALIZE ICG ICGC1 = $38 ICGC2 = $00 CHECK FLL LOCK STATUS.
Chapter 8 Internal Clock Generator (S08ICGV4) 8.5.3 Example #2: External Crystal = 4 MHz, Bus Frequency = 20 MHz In this example, the FLL will be used (in FEE mode) to multiply the external 4 MHz oscillator up to 40-MHz to achieve 20 MHz bus frequency. After the MCU is released from reset, the ICG is in self-clocked mode (SCM) and supplies approximately 8 MHz on ICGOUT which corresponds to a 4 MHz bus frequency (fBus).
Chapter 8 Internal Clock Generator (S08ICGV4) RECOVERY FROM STOP RESET INITIALIZE ICG ICGC1 = $7A ICGC2 = $30 CHECK FLL LOCK STATUS LOCK = 1? YES SERVICE INTERRUPT SOURCE (fBus = 4 MHz) NO CHECK FLL LOCK STATUS LOCK = 1? NO YES CONTINUE CONTINUE Figure 8-15.
Chapter 8 Internal Clock Generator (S08ICGV4) 8.5.4 Example #3: No External Crystal Connection, 5.4 MHz Bus Frequency In this example, the FLL will be used (in FEI mode) to multiply the internal 243 kHz (approximate) reference clock up to 10.8 MHz to achieve 5.4 MHz bus frequency. This system will also use the trim function to fine tune the frequency based on an external reference signal.
Chapter 8 Internal Clock Generator (S08ICGV4) ICGTRM = $xx Bit 7:0 TRIM Only need to write when trimming internal oscillator; done in separate operation (see example #4) RECOVERY FROM STOP RESET INITIALIZE ICG ICGC1 = $28 ICGC2 = $31 CHECK FLL LOCK STATUS. LOCK = 1? CHECK FLL LOCK STATUS. LOCK = 1? NO YES NO CONTINUE YES CONTINUE NOTE: THIS WILL REQUIRE THE INTERAL REFERENCE CLOCK TO START AND STABILIZE. Figure 8-16.
Chapter 8 Internal Clock Generator (S08ICGV4) 8.5.5 Example #4: Internal Clock Generator Trim The internally generated clock source is guaranteed to have a period ± 25% of the nominal value. In some cases, this may be sufficient accuracy. For other applications that require a tight frequency tolerance, a trimming procedure is provided that will allow a very accurate source. This section outlines one example of trimming the internal oscillator.
Chapter 8 Internal Clock Generator (S08ICGV4) MC9S08AW60 Data Sheet, Rev 2 156 Freescale Semiconductor
Chapter 9 Keyboard Interrupt (S08KBIV1) 9.1 Introduction The MC9S08AW60 Series has one KBI module with eight keyboard interrupt inputs that are shared with port D and port G pins. See Chapter 2, “Pins and Connections,” for more information about the logic and hardware aspects of these pins. 9.2 Keyboard Pin Sharing The KBI input KBIP7 shares a common pin with PTD7 and AD15. When KBIP7 is enabled the pin is forced to its input state regardless of the value of the associated port D data direction bit.
Chapter 9 Keyboard Interrupt (S08KBIV1) 9.
HCS08 CORE BDC DEBUG MODULE (DBG) RTI COP IRQ LVD SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) IIC MODULE (IIC1) 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC1) TxD2 SDA1 SCL1 6-CHANNEL TIMER/PWM MODULE (TPM1) INTERNAL CLOCK GENERATOR (ICG) LOW-POWER OSCILLATOR SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) VOLTAGE REGULATOR 2-CHANNEL TIMER/PWM MODULE (TPM2) SPSCK1 MOSI1 PTE7/SPSCK1 MISO1 SS1 TPM1CLK TPM1CH5– TPM1CH0 RxD1 TxD1 PORT E USER RAM AW60/48/32 = 2048 BYTES AW16 = 1024 BYTES PTD7/AD1
Chapter 9 Keyboard Interrupt (S08KBIV1) 9.3.1 KBI Block Diagram Figure 9-2 shows the block diagram for a KBI module. KBI1P0 KBIPE0 KBIPE3 VDD 0 SYNCHRONIZER S KBIPE4 KEYBOARD INTERRUPT FF STOP STOP BYPASS KEYBOARD INTERRUPT REQUEST KBIMOD 1 0 KBF CK KBEDG4 KBI1Pn RESET D CLR Q 1 KBI1P4 BUSCLK KBACK KBI1P3 KBIE S KBIPEn KBEDGn Figure 9-2. KBI Block Diagram 9.
Chapter 9 Keyboard Interrupt (S08KBIV1) 9.4.1 KBI Status and Control Register (KBI1SC) 7 6 5 4 KBEDG7 KBEDG6 KBEDG5 KBEDG4 R 3 2 KBF 0 W Reset 1 0 KBIE KBIMOD 0 0 KBACK 0 0 0 0 0 0 = Unimplemented or Reserved Figure 9-3. KBI Status and Control Register (KBI1SC) Table 9-2.
Chapter 9 Keyboard Interrupt (S08KBIV1) 9.4.2 KBI Pin Enable Register (KBI1PE) 7 6 5 4 3 2 1 0 KBIPE7 KBIPE6 KBIPE5 KBIPE4 KBIPE3 KBIPE2 KBIPE1 KBIPE0 0 0 0 0 0 0 0 0 R W Reset = Unimplemented or Reserved Figure 9-4. KBI Pin Enable Register (KBI1PE) Table 9-3. KBI1PE Register Field Descriptions Field Description 7:0 KBIPE[7:0] 9.5 9.5.
Chapter 9 Keyboard Interrupt (S08KBIV1) 9.5.3 KBI Interrupt Controls The KBF status flag becomes set (1) when an edge event has been detected on any KBI input pin. If KBIE = 1 in the KBI1SC register, a hardware interrupt will be requested whenever KBF = 1. The KBF flag is cleared by writing a 1 to the keyboard acknowledge (KBACK) bit. When KBIMOD = 0 (selecting edge-only operation), KBF is always cleared by writing 1 to KBACK.
Chapter 9 Keyboard Interrupt (S08KBIV1) MC9S08AW60 Data Sheet, Rev 2 164 Freescale Semiconductor
Chapter 10 Timer/PWM (S08TPMV2) 10.1 Introduction The MC9S08AW60 Series includes two independent timer/PWM (TPM) modules which support traditional input capture, output compare, or buffered edge-aligned pulse-width modulation (PWM) on each channel. A control bit in each TPM configures all channels in that timer to operate as center-aligned PWM functions.
HCS08 CORE BDC DEBUG MODULE (DBG) RTI COP IRQ LVD SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) IIC MODULE (IIC1) 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC1) TxD2 SDA1 SCL1 INTERNAL CLOCK GENERATOR (ICG) 6-CHANNEL TIMER/PWM MODULE (TPM1) LOW-POWER OSCILLATOR SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) VOLTAGE REGULATOR 2-CHANNEL TIMER/PWM MODULE (TPM2) SPSCK1 MOSI1 PTE7/SPSCK1 MISO1 SS1 TPM1CLK TPM1CH5– TPM1CH0 RxD1 TxD1 PORT E USER RAM AW60/48/32 = 2048 BYTES AW16 = 1024 BYTES PTD7/AD
Chapter 10 Timer/Pulse-Width Modulator (S08TPMV2) 10.2.
Chapter 10 Timer/Pulse-Width Modulator (S08TPMV2) BUSCLK XCLK TPMxCLK SYNC CLOCK SOURCE SELECT OFF, BUS, XCLK, EXT CLKSB PRESCALE AND SELECT DIVIDE BY 1, 2, 4, 8, 16, 32, 64, or 128 PS2 CLKSA PS1 PS0 CPWMS MAIN 16-BIT COUNTER TOF COUNTER RESET INTERRUPT LOGIC TOIE 16-BIT COMPARATOR TPMxMODH:TPMxMODL CHANNEL 0 ELS0B ELS0A PORT LOGIC 16-BIT COMPARATOR TPMxC0VH:TPMxC0VL CH0F INTERRUPT LOGIC 16-BIT LATCH INTERNAL BUS CHANNEL 1 MS0B MS0A ELS1B ELS1A CH0IE TPMxCH1 PORT LOGIC 16-BIT CO
Chapter 10 Timer/Pulse-Width Modulator (S08TPMV2) All TPM channels are programmable independently as input capture, output compare, or buffered edge-aligned PWM channels. 10.3 External Signal Description When any pin associated with the timer is configured as a timer input, a passive pullup can be enabled. After reset, the TPM modules are disabled and all pins default to general-purpose inputs with the passive pullups disabled. 10.3.
Chapter 10 Timer/Pulse-Width Modulator (S08TPMV2) Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. Some MCU systems have more than one TPM, so register names include placeholder characters to identify which TPM and which channel is being referenced. For example, TPMxCnSC refers to timer (TPM) x, channel n and TPM1C2SC is the status and control register for timer 1, channel 2. 10.4.
Chapter 10 Timer/Pulse-Width Modulator (S08TPMV2) Table 10-2. TPM Clock Source Selection CLKSB:CLKSA TPM Clock Source to Prescaler Input 0:0 No clock selected (TPMx disabled) 0:1 Bus rate clock (BUSCLK) 1:0 Fixed system clock (XCLK) 1:1 External source (TPMxCLK)1,2 1 The maximum frequency that is allowed as an external clock is one-fourth of the bus frequency.
Chapter 10 Timer/Pulse-Width Modulator (S08TPMV2) R 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 W Reset Any write to TPMxCNTL clears the 16-bit counter. 0 0 0 0 0 0 Figure 10-5.
Chapter 10 Timer/Pulse-Width Modulator (S08TPMV2) 10.4.4 Timer x Channel n Status and Control Register (TPMxCnSC) TPMxCnSC contains the channel interrupt status flag and control bits that are used to configure the interrupt enable, channel configuration, and pin function. 7 6 5 4 3 2 CHnF CHnIE MSnB MSnA ELSnB ELSnA 0 0 0 0 0 0 R 1 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 10-8. Timer x Channel n Status and Control Register (TPMxCnSC) Table 10-4.
Chapter 10 Timer/Pulse-Width Modulator (S08TPMV2) Table 10-5.
Chapter 10 Timer/Pulse-Width Modulator (S08TPMV2) In output compare or PWM modes, writing to either byte (TPMxCnVH or TPMxCnVL) latches the value into a buffer. When both bytes have been written, they are transferred as a coherent 16-bit value into the timer channel value registers. This latching mechanism may be manually reset by writing to the TPMxCnSC register. This latching mechanism allows coherent 16-bit writes in either order, which is friendly to various compiler implementations. 10.
Chapter 10 Timer/Pulse-Width Modulator (S08TPMV2) When center-aligned PWM operation is specified, the counter counts upward from 0x0000 through its terminal count and then counts downward to 0x0000 where it returns to up-counting. Both 0x0000 and the terminal count value (value in TPMxMODH:TPMxMODL) are normal length counts (one timer clock period long). An interrupt flag and enable are associated with the main 16-bit counter.
Chapter 10 Timer/Pulse-Width Modulator (S08TPMV2) 10.5.2.2 Output Compare Mode With the output compare function, the TPM can generate timed pulses with programmable position, polarity, duration, and frequency. When the counter reaches the value in the channel value registers of an output compare channel, the TPM can set, clear, or toggle the channel pin.
Chapter 10 Timer/Pulse-Width Modulator (S08TPMV2) 10.5.3 Center-Aligned PWM Mode This type of PWM output uses the up-/down-counting mode of the timer counter (CPWMS = 1). The output compare value in TPMxCnVH:TPMxCnVL determines the pulse width (duty cycle) of the PWM signal and the period is determined by the value in TPMxMODH:TPMxMODL. TPMxMODH:TPMxMODL should be kept in the range of 0x0001 to 0x7FFF because values outside this range can produce ambiguous results.
Chapter 10 Timer/Pulse-Width Modulator (S08TPMV2) transferred to the corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have been written and the timer counter overflows (reverses direction from up-counting to down-counting at the end of the terminal count in the modulus register). This TPMxCNT overflow requirement only applies to PWM channels, not output compares.
Chapter 10 Timer/Pulse-Width Modulator (S08TPMV2) 10.6.3 Channel Event Interrupt Description The meaning of channel interrupts depends on the current mode of the channel (input capture, output compare, edge-aligned PWM, or center-aligned PWM). When a channel is configured as an input capture channel, the ELSnB:ELSnA control bits select rising edges, falling edges, any edge, or no edge (off) as the edge that triggers an input capture event. When the selected edge is detected, the interrupt flag is set.
Chapter 11 Serial Communications Interface (S08SCIV2) 11.1 Introduction The MC9S08AW60 Series includes two independent serial communications interface (SCI) modules which are sometimes called universal asynchronous receiver/transmitters (UARTs). Typically, these systems are used to connect to the RS232 serial input/output (I/O) port of a personal computer or workstation, but they can also be used to communicate with other embedded controllers.
HCS08 CORE BDC DEBUG MODULE (DBG) RTI COP IRQ LVD SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) IIC MODULE (IIC1) 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC1) TxD2 SDA1 SCL1 INTERNAL CLOCK GENERATOR (ICG) 6-CHANNEL TIMER/PWM MODULE (TPM1) LOW-POWER OSCILLATOR SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) VOLTAGE REGULATOR 2-CHANNEL TIMER/PWM MODULE (TPM2) SPSCK1 MOSI1 PTE7/SPSCK1 MISO1 SS1 TPM1CLK TPM1CH5– TPM1CH0 RxD1 TxD1 PORT E USER RAM AW60/48/32 = 2048 BYTES AW16 = 1024 BYTES PTD7/AD
Chapter 11 Serial Communications Interface (S08SCIV2) 11.1.
Chapter 11 Serial Communications Interface (S08SCIV2) INTERNAL BUS (WRITE-ONLY) LOOPS SCID – Tx BUFFER 8 7 6 5 4 3 2 1 PREAMBLE (ALL 1s) PARITY GENERATION PT SHIFT ENABLE PE LOAD FROM SCIxD SHIFT DIRECTION T8 0 START TO RECEIVE DATA IN L TO TxD PIN LSB H 1 × BAUD RATE CLOCK 11-BIT TRANSMIT SHIFT REGISTER LOOP CONTROL TXINV BREAK (ALL 0s) STOP M RSRC SCI CONTROLS TxD TE SBK TRANSMIT CONTROL TXDIR TxD DIRECTION TO TxD PIN LOGIC BRK13 TDRE TIE TC Tx INTERRUPT REQUEST TC
Chapter 11 Serial Communications Interface (S08SCIV2) Figure 11-3 shows the receiver portion of the SCI.
Chapter 11 Serial Communications Interface (S08SCIV2) Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all SCI registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 11.2.
Chapter 11 Serial Communications Interface (S08SCIV2) 11.2.2 SCI Control Register 1 (SCIxC1) This read/write register is used to control various optional features of the SCI system. 7 6 5 4 3 2 1 0 LOOPS SCISWAI RSRC M WAKE ILT PE PT 0 0 0 0 0 0 0 0 R W Reset Figure 11-6. SCI Control Register 1 (SCIxC1) Table 11-3. SCIxC1 Register Field Descriptions Field 7 LOOPS Description Loop Mode Select — Selects between loop back modes and normal 2-pin full-duplex modes.
Chapter 11 Serial Communications Interface (S08SCIV2) 11.2.3 SCI Control Register 2 (SCIxC2) This register can be read or written at any time. 7 6 5 4 3 2 1 0 TIE TCIE RIE ILIE TE RE RWU SBK 0 0 0 0 0 0 0 0 R W Reset Figure 11-7. SCI Control Register 2 (SCIxC2) Table 11-4. SCIxC2 Register Field Descriptions Field 7 TIE 6 TCIE Description Transmit Interrupt Enable (for TDRE) 0 Hardware interrupts from TDRE disabled (use polling).
Chapter 11 Serial Communications Interface (S08SCIV2) Table 11-4. SCIxC2 Register Field Descriptions (continued) Field Description 1 RWU Receiver Wakeup Control — This bit can be written to 1 to place the SCI receiver in a standby state where it waits for automatic hardware detection of a selected wakeup condition. The wakeup condition is either an idle line between messages (WAKE = 0, idle-line wakeup), or a logic 1 in the most significant data bit in a character (WAKE = 1, address-mark wakeup).
Chapter 11 Serial Communications Interface (S08SCIV2) Table 11-5. SCIxS1 Register Field Descriptions (continued) Field Description 5 RDRF Receive Data Register Full Flag — RDRF becomes set when a character transfers from the receive shifter into the receive data register (SCIxD). In 8-bit mode, to clear RDRF, read SCIxS1 with RDRF = 1 and then read the SCI data register (SCIxD). In 9-bit mode, to clear RDRF, read SCIxS1 with RDRF = 1 and then read SCIxD and the SCI control 3 register (SCIxC3).
Chapter 11 Serial Communications Interface (S08SCIV2) 11.2.5 SCI Status Register 2 (SCIxS2) This register has one read-only status flag. Writes have no effect. R 7 6 5 4 3 0 0 0 0 0 2 1 0 0 RAF 0 0 BRK13 W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 11-9. SCI Status Register 2 (SCIxS2) Table 11-6. SCIxS2 Register Field Descriptions Field 2 BRK13 0 RAF 11.2.6 Description Break Character Length — BRK13 is used to select a longer break character length.
Chapter 11 Serial Communications Interface (S08SCIV2) Table 11-7. SCIxC3 Register Field Descriptions (continued) Field 1 Description 5 TXDIR TxD Pin Direction in Single-Wire Mode — When the SCI is configured for single-wire half-duplex operation (LOOPS = RSRC = 1), this bit determines the direction of data at the TxD pin. 0 TxD pin is an input in single-wire mode. 1 TxD pin is an output in single-wire mode.
Chapter 11 Serial Communications Interface (S08SCIV2) 11.3.1 Baud Rate Generation As shown in Figure 11-12, the clock source for the SCI baud rate generator is the bus-rate clock. MODULO DIVIDE BY (1 THROUGH 8191) BUSCLK SBR12:SBR0 BAUD RATE GENERATOR OFF IF [SBR12:SBR0] = 0 DIVIDE BY 16 Tx BAUD RATE Rx SAMPLING CLOCK (16 × BAUD RATE) BAUD RATE = BUSCLK [SBR12:SBR0] × 16 Figure 11-12.
Chapter 11 Serial Communications Interface (S08SCIV2) If no new character is waiting in the transmit data buffer after a stop bit is shifted out the TxD pin, the transmitter sets the transmit complete flag and enters an idle mode, with TxD high, waiting for more characters to transmit. Writing 0 to TE does not immediately release the pin to be a general-purpose I/O pin. Any transmit activity that is in progress must first be completed.
Chapter 11 Serial Communications Interface (S08SCIV2) to Section 11.3.5.1, “8- and 9-Bit Data Modes.” For the remainder of this discussion, we assume the SCI is configured for normal 8-bit data mode. After receiving the stop bit into the receive shifter, and provided the receive data register is not already full, the data character is transferred to the receive data register and the receive data register full (RDRF) status flag is set.
Chapter 11 Serial Communications Interface (S08SCIV2) character(s) of each message, and as soon as they determine the message is intended for a different receiver, they write logic 1 to the receiver wake up (RWU) control bit in SCIxC2. When RWU = 1, it inhibits setting of the status flags associated with the receiver, thus eliminating the software overhead for handling the unimportant message characters.
Chapter 11 Serial Communications Interface (S08SCIV2) systems with modems to determine when it is safe to turn off the modem. If the transmit complete interrupt enable (TCIE) bit is set, a hardware interrupt will be requested whenever TC = 1. Instead of hardware interrupts, software polling may be used to monitor the TDRE and TC status flags if the corresponding TIE or TCIE local interrupt masks are 0s.
Chapter 11 Serial Communications Interface (S08SCIV2) 9-bit data mode typically is used in conjunction with parity to allow eight bits of data plus the parity in the ninth bit. Or it is used with address-mark wakeup so the ninth data bit can serve as the wakeup bit. In custom protocols, the ninth bit can also serve as a software-controlled marker. 11.3.5.2 Stop Mode Operation During all stop modes, clocks to the SCI module are halted.
Chapter 12 Serial Peripheral Interface (S08SPIV3) The MC9S08AW60 Series has one serial peripheral interface (SPI) module. The four pins associated with SPI functionality are shared with port E pins 4–7. See Appendix A, “Electrical Characteristics and Timing Specifications,” for SPI electrical parametric information.
HCS08 CORE BDC DEBUG MODULE (DBG) RTI COP IRQ LVD SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) IIC MODULE (IIC1) 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC1) TxD2 SDA1 SCL1 INTERNAL CLOCK GENERATOR (ICG) 6-CHANNEL TIMER/PWM MODULE (TPM1) LOW-POWER OSCILLATOR SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) VOLTAGE REGULATOR 2-CHANNEL TIMER/PWM MODULE (TPM2) SPSCK1 MOSI1 PTE7/SPSCK1 MISO1 SS1 TPM1CLK TPM1CH5– TPM1CH0 RxD1 TxD1 PORT E USER RAM AW60/48/32 = 2048 BYTES AW16 = 1024 BYTES PTD7/AD
Chapter 12 Serial Peripheral Interface (S08SPIV3) 12.0.1 Features Features of the SPI module include: • Master or slave mode operation • Full-duplex or single-wire bidirectional option • Programmable transmit bit rate • Double-buffered transmit and receive • Serial clock phase and polarity options • Slave select output • Selectable MSB-first or LSB-first shifting 12.0.
Chapter 12 Serial Peripheral Interface (S08SPIV3) The most common uses of the SPI system include connecting simple shift registers for adding input or output ports or connecting small peripheral devices such as serial A/D or D/A converters. Although Figure 12-2 shows a system where data is exchanged between two MCUs, many practical systems involve simpler connections where data is unidirectionally transferred from the master MCU to a slave or from a slave to the master MCU. 12.0.2.
Chapter 12 Serial Peripheral Interface (S08SPIV3) PIN CONTROL M SPE MOSI (MOMI) S Tx BUFFER (WRITE SPI1D) ENABLE SPI SYSTEM M SHIFT OUT SPI SHIFT REGISTER SHIFT IN MISO (SISO) S SPC0 Rx BUFFER (READ SPI1D) BIDIROE SHIFT DIRECTION LSBFE SHIFT CLOCK Rx BUFFER FULL Tx BUFFER EMPTY MASTER CLOCK BUS RATE CLOCK SPIBR CLOCK GENERATOR MSTR CLOCK LOGIC SLAVE CLOCK MASTER/SLAVE M SPSCK S MASTER/ SLAVE MODE SELECT MODFEN SSOE MODE FAULT DETECTION SS SPRF SPTEF SPTIE MODF SPIE SPI INTERRUPT
Chapter 12 Serial Peripheral Interface (S08SPIV3) BUS CLOCK PRESCALER CLOCK RATE DIVIDER DIVIDE BY 1, 2, 3, 4, 5, 6, 7, or 8 DIVIDE BY 2, 4, 8, 16, 32, 64, 128, or 256 SPPR2:SPPR1:SPPR0 SPR2:SPR1:SPR0 MASTER SPI BIT RATE Figure 12-4. SPI Baud Rate Generation 12.1 External Signal Description The SPI optionally shares four port pins. The function of these pins depends on the settings of SPI control bits.
Chapter 12 Serial Peripheral Interface (S08SPIV3) 12.2 Modes of Operation 12.2.1 SPI in Stop Modes The SPI is disabled in all stop modes, regardless of the settings before executing the STOP instruction. During either stop1 or stop2 mode, the SPI module will be fully powered down. Upon wake-up from stop1 or stop2 mode, the SPI module will be in the reset state. During stop3 mode, clocks to the SPI module are halted. No registers are affected.
Chapter 12 Serial Peripheral Interface (S08SPIV3) Table 12-1. SPI1C1 Field Descriptions (continued) Field Description 4 MSTR Master/Slave Mode Select 0 SPI module configured as a slave SPI device 1 SPI module configured as a master SPI device 3 CPOL Clock Polarity — This bit effectively places an inverter in series with the clock signal from a master SPI or to a slave SPI device. Refer to Section 12.4.1, “SPI Clock Formats” for more details.
Chapter 12 Serial Peripheral Interface (S08SPIV3) Table 12-3. SPI1C2 Register Field Descriptions Field Description 4 MODFEN Master Mode-Fault Function Enable — When the SPI is configured for slave mode, this bit has no meaning or effect. (The SS pin is the slave select input.) In master mode, this bit determines how the SS pin is used (refer to Table 12-2 for more details).
Chapter 12 Serial Peripheral Interface (S08SPIV3) Table 12-5. SPI Baud Rate Prescaler Divisor SPPR2:SPPR1:SPPR0 Prescaler Divisor 0:0:0 1 0:0:1 2 0:1:0 3 0:1:1 4 1:0:0 5 1:0:1 6 1:1:0 7 1:1:1 8 Table 12-6. SPI Baud Rate Divisor 12.3.4 SPR2:SPR1:SPR0 Rate Divisor 0:0:0 2 0:0:1 4 0:1:0 8 0:1:1 16 1:0:0 32 1:0:1 64 1:1:0 128 1:1:1 256 SPI Status Register (SPI1S) This register has three read-only status bits. Bits 6, 3, 2, 1, and 0 are not implemented and always read 0.
Chapter 12 Serial Peripheral Interface (S08SPIV3) Table 12-7. SPI1S Register Field Descriptions Field Description 7 SPRF SPI Read Buffer Full Flag — SPRF is set at the completion of an SPI transfer to indicate that received data may be read from the SPI data register (SPI1D). SPRF is cleared by reading SPRF while it is set, then reading the SPI data register.
Chapter 12 Serial Peripheral Interface (S08SPIV3) 12.4 Functional Description An SPI transfer is initiated by checking for the SPI transmit buffer empty flag (SPTEF = 1) and then writing a byte of data to the SPI data register (SPI1D) in the master SPI device.
Chapter 12 Serial Peripheral Interface (S08SPIV3) pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1). The master SS output goes to active low one-half SPSCK cycle before the start of the transfer and goes back high at the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a slave. BIT TIME # (REFERENCE) 1 2 ...
Chapter 12 Serial Peripheral Interface (S08SPIV3) in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave.
Chapter 12 Serial Peripheral Interface (S08SPIV3) 12.4.2 SPI Interrupts There are three flag bits, two interrupt mask bits, and one interrupt vector associated with the SPI system. The SPI interrupt enable mask (SPIE) enables interrupts from the SPI receiver full flag (SPRF) and mode fault flag (MODF). The SPI transmit interrupt enable mask (SPTIE) enables interrupts from the SPI transmit buffer empty flag (SPTEF).
Chapter 12 Serial Peripheral Interface (S08SPIV3) MC9S08AW60 Data Sheet, Rev 2 214 Freescale Semiconductor
Chapter 13 Inter-Integrated Circuit (S08IICV1) 13.1 Introduction The MC9S08AW60 Series of microcontrollers has an inter-integrated circuit (IIC) module for communication with other integrated circuits. The two pins associated with this module, SCL and SDA, are open-drain outputs and are shared with port C pins 0 and 1, respectively.
HCS08 CORE BDC DEBUG MODULE (DBG) RTI COP IRQ LVD SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) IIC MODULE (IIC1) 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC1) TxD2 SDA1 SCL1 INTERNAL CLOCK GENERATOR (ICG) 6-CHANNEL TIMER/PWM MODULE (TPM1) LOW-POWER OSCILLATOR SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) VOLTAGE REGULATOR 2-CHANNEL TIMER/PWM MODULE (TPM2) SPSCK1 MOSI1 PTE7/SPSCK1 MISO1 SS1 TPM1CLK TPM1CH5– TPM1CH0 RxD1 TxD1 PORT E USER RAM AW60/48/32 = 2048 BYTES AW16 = 1024 BYTES PTD7/AD
Chapter 13 Inter-Integrated Circuit (S08IICV1) 13.1.
Chapter 13 Inter-Integrated Circuit (S08IICV1) 13.1.3 Block Diagram Figure 13-2 is a block diagram of the IIC. ADDRESS DATA BUS INTERRUPT ADDR_DECODE CTRL_REG DATA_MUX FREQ_REG ADDR_REG STATUS_REG DATA_REG INPUT SYNC START STOP ARBITRATION CONTROL CLOCK CONTROL IN/OUT DATA SHIFT REGISTER ADDRESS COMPARE SCL SDA Figure 13-2. IIC Functional Block Diagram 13.2 External Signal Description This section describes each user-accessible pin signal. 13.2.
Chapter 13 Inter-Integrated Circuit (S08IICV1) Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all IIC registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 13.3.
Chapter 13 Inter-Integrated Circuit (S08IICV1) Table 13-2. IIC1A Register Field Descriptions Field Description 7:6 MULT IIC Multiplier Factor — The MULT bits define the multiplier factor mul. This factor is used along with the SCL divider to generate the IIC baud rate. The multiplier factor mul as defined by the MULT bits is provided below. 00 mul = 01 01 mul = 02 10 mul = 04 11 Reserved 5:0 ICR IIC Clock Rate — The ICR bits are used to prescale the bus clock for bit rate selection.
Chapter 13 Inter-Integrated Circuit (S08IICV1) Table 13-3.
Chapter 13 Inter-Integrated Circuit (S08IICV1) 13.3.3 IIC Control Register (IIC1C) 7 6 5 4 3 IICEN IICIE MST TX TXAK R W Reset 2 1 0 0 0 0 0 0 RSTA 0 0 0 0 0 0 = Unimplemented or Reserved Figure 13-5. IIC Control Register (IIC1C) Table 13-4. IIC1C Register Field Descriptions Field Description 7 IICEN IIC Enable — The IICEN bit determines whether the IIC module is enabled. 0 IIC is not enabled. 1 IIC is enabled.
Chapter 13 Inter-Integrated Circuit (S08IICV1) 13.3.4 IIC Status Register (IIC1S) 7 R 6 TCF 5 4 BUSY IAAS 3 2 0 SRW ARBL 1 0 RXAK IICIF W Reset 1 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 13-6. IIC Status Register (IIC1S) Table 13-5. IIC1S Register Field Descriptions Field Description 7 TCF Transfer Complete Flag — This bit is set on the completion of a byte transfer.
Chapter 13 Inter-Integrated Circuit (S08IICV1) 13.3.5 IIC Data I/O Register (IIC1D) 7 6 5 4 3 2 1 0 0 0 0 0 R DATA W Reset 0 0 0 0 Figure 13-7. IIC Data I/O Register (IIC1D) Table 13-6. IIC1D Register Field Descriptions Field Description 7:0 DATA Data — In master transmit mode, when data is written to the IIC1D, a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data.
Chapter 13 Inter-Integrated Circuit (S08IICV1) 13.4 Functional Description This section provides a complete functional description of the IIC module. 13.4.1 IIC Protocol The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices connected to it must have open drain or open collector outputs. A logic AND function is exercised on both lines with external pull-up resistors. The value of these resistors is system dependent.
Chapter 13 Inter-Integrated Circuit (S08IICV1) 13.4.1.1 START Signal When the bus is free; i.e., no master device is engaging the bus (both SCL and SDA lines are at logical high), a master may initiate communication by sending a START signal. As shown in Figure 13-8, a START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states.
Chapter 13 Inter-Integrated Circuit (S08IICV1) 13.4.1.4 STOP Signal The master can terminate the communication by generating a STOP signal to free the bus. However, the master may generate a START signal followed by a calling command without generating a STOP signal first. This is called repeated START. A STOP signal is defined as a low-to-high transition of SDA while SCL at logical 1 (see Figure 13-8).
Chapter 13 Inter-Integrated Circuit (S08IICV1) DELAY START COUNTING HIGH PERIOD SCL1 SCL2 SCL INTERNAL COUNTER RESET Figure 13-9. IIC Clock Synchronization 13.4.1.8 Handshaking The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line. 13.4.1.
Chapter 13 Inter-Integrated Circuit (S08IICV1) 13.6.1 Byte Transfer Interrupt The TCF (transfer complete flag) bit is set at the falling edge of the 9th clock to indicate the completion of byte transfer. 13.6.2 Address Detect Interrupt When the calling address matches the programmed slave address (IIC address register), the IAAS bit in the status register is set. The CPU is interrupted provided the IICIE is set. The CPU must check the SRW bit and set its Tx mode accordingly. 13.6.
Chapter 13 Inter-Integrated Circuit (S08IICV1) 13.7 1. 2. 3. 4. 1. 2. 3. 4. 5. 6. 7.
Chapter 13 Inter-Integrated Circuit (S08IICV1) Clear IICIF Master Mode ? Y TX N Y RX Tx/Rx ? Arbitration Lost ? N Last Byte Transmitted ? N Clear ARBL Y RXAK=0 ? Last Byte to Be Read ? N N N Y Y IAAS=1 ? Y IAAS=1 ? Y N Address Transfer Y End of Addr Cycle (Master Rx) ? Y Y (Read) 2nd Last Byte to Be Read ? N SRW=1 ? Write Next Byte to IICD Set TXACK =1 Generate Stop Signal (MST = 0) Switch to Rx Mode Generate Stop Signal (MST = 0) Read Data from IICD and Store ACK from
Chapter 13 Inter-Integrated Circuit (S08IICV1) MC9S08AW60 Data Sheet, Rev 2 232 Freescale Semiconductor
Chapter 14 Analog-to-Digital Converter (S08ADC10V1) 14.1 Overview The 10-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation within an integrated microcontroller system-on-chip. The ADC module design supports up to 28 separate analog inputs (AD0-AD27). Only 18 (AD0-AD15, AD26, and AD27) of the possible inputs are implemented on the MC9S08AW60 Series of MCUs. These inputs are selected by the ADCH bits. Some inputs are shared with I/O pins as shown in Figure 14-1.
Chapter 14 Analog-to-Digital Converter (S08ADC10V1) Table 14-1. ADC Channel Assignment (continued) 1 ADCH Channel Input Pin Control ADCH Channel Input Pin Control 01110 AD14 PTD6/ADC1P14/ TPM1CLK ADPC14 11110 VREFL VREFL N/A 01111 AD15 PTD7ADC1P15/ KBI1P7 ADPC15 11111 Module disabled None N/A For more information, see Section 14.2.3, “Temperature Sensor.” NOTE Selecting the internal bandgap channel requires BGBE =1 in SPMSC1 see Section 5.9.
Chapter 14 Analog-to-Digital Converter (S08ADC10V1) 14.2.2.1 Analog Pin Enables The ADC on MC9S08AW60 Series contains only two analog pin enable registers, APCTL1 and APCTL2. 14.2.2.2 Low-Power Mode Operation The ADC is capable of running in stop3 mode but requires LVDSE and LVDE in SPMSC1 to be set. 14.2.3 Temperature Sensor The ADC1 module includes a temperature sensor whose output is connected to one of the ADC analog channel inputs.
HCS08 CORE BDC DEBUG MODULE (DBG) RTI COP IRQ LVD SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) IIC MODULE (IIC1) 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC1) TxD2 SDA1 SCL1 LOW-POWER OSCILLATOR SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) VOLTAGE REGULATOR 2-CHANNEL TIMER/PWM MODULE (TPM2) PTE7/SPSCK1 MISO1 SS1 TPM1CLK TPM1CH5– TPM1CH0 RxD1 TxD1 PORT E INTERNAL CLOCK GENERATOR (ICG) 6-CHANNEL TIMER/PWM MODULE (TPM1) SPSCK1 MOSI1 6 TPM2CLK PORT F USER RAM AW60/48/32 = 2048 BYTES AW16 =
Chapter 14 Analog-to-Digital Converter (S08ADC10V1) 14.2.4 Features Features of the ADC module include: • Linear successive approximation algorithm with 10 bits resolution. • Up to 28 analog inputs. • Output formatted in 10- or 8-bit right-justified format. • Single or continuous conversion (automatic return to idle after single conversion). • Configurable sample time and conversion speed/power. • Conversion complete flag and interrupt. • Input clock selectable from up to four sources.
Chapter 14 Analog-to-Digital Converter (S08ADC10V1) ADIV ADLPC MODE ADLSMP ADTRG 2 ADCO ADCH 1 ADC1CFG complete COCO ADC1SC1 ADICLK Compare true AIEN 3 Async Clock Gen ADACK MCU STOP ADCK ÷2 ALTCLK abort transfer sample initialize ••• AD0 convert Control Sequencer ADHWT Bus Clock Clock Divide AIEN 1 Interrupt COCO 2 ADVIN SAR Converter AD27 VREFH Data Registers Sum VREFL Compare true 3 Compare Value Registers ACFGT Value Compare Logic ADC1SC2 Figure 14-2.
Chapter 14 Analog-to-Digital Converter (S08ADC10V1) 14.3.1 Analog Power (VDDAD) The ADC analog portion uses VDDAD as its power connection. In some packages, VDDAD is connected internally to VDD. If externally available, connect the VDDAD pin to the same voltage potential as VDD. External filtering may be necessary to ensure clean VDDAD for good results. 14.3.2 Analog Ground (VSSAD) The ADC analog portion uses VSSAD as its ground connection. In some packages, VSSAD is connected internally to VSS.
Chapter 14 Analog-to-Digital Converter (S08ADC10V1) 7 R 6 5 4 AIEN ADCO 0 0 3 2 1 0 1 1 COCO ADCH W Reset: 0 1 1 1 = Unimplemented or Reserved Figure 14-3. Status and Control Register (ADC1SC1) Table 14-3. ADC1SC1 Register Field Descriptions Field Description 7 COCO Conversion Complete Flag — The COCO flag is a read-only bit which is set each time a conversion is completed when the compare function is disabled (ACFE = 0).
Chapter 14 Analog-to-Digital Converter (S08ADC10V1) Figure 14-4. Input Channel Select (continued) 14.4.
Chapter 14 Analog-to-Digital Converter (S08ADC10V1) Table 14-4. ADC1SC2 Register Field Descriptions (continued) Field Description 5 ACFE Compare Function Enable — ACFE is used to enable the compare function. 0 Compare function disabled 1 Compare function enabled 4 ACFGT Compare Function Greater Than Enable — ACFGT is used to configure the compare function to trigger when the result of the conversion of the input being monitored is greater than or equal to the compare value.
Chapter 14 Analog-to-Digital Converter (S08ADC10V1) R 7 6 5 4 3 2 1 0 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 0 0 0 0 0 0 0 0 W Reset: = Unimplemented or Reserved Figure 14-7. Data Result Low Register (ADC1RL) 14.4.5 Compare Value High Register (ADC1CVH) This register holds the upper two bits of the 10-bit compare value. These bits are compared to the upper two bits of the result following a conversion in 10-bit mode when the compare function is enabled.
Chapter 14 Analog-to-Digital Converter (S08ADC10V1) 7 6 5 4 3 2 1 0 R ADLPC ADIV ADLSMP MODE ADICLK W Reset: 0 0 0 0 0 0 0 0 Figure 14-10. Configuration Register (ADC1CFG) Table 14-5. ADC1CFG Register Field Descriptions Field Description 7 ADLPC Low Power Configuration — ADLPC controls the speed and power configuration of the successive approximation converter. This is used to optimize power consumption when higher sample rates are not required.
Chapter 14 Analog-to-Digital Converter (S08ADC10V1) Table 14-8. Input Clock Select ADICLK 14.4.8 Selected Clock Source 00 Bus clock 01 Bus clock divided by 2 10 Alternate clock (ALTCLK) 11 Asynchronous clock (ADACK) Pin Control 1 Register (APCTL1) The pin control registers are used to disable the I/O port control of MCU pins used as analog inputs. APCTL1 is used to control the pins associated with channels 0–7 of the ADC module.
Chapter 14 Analog-to-Digital Converter (S08ADC10V1) Table 14-9. APCTL1 Register Field Descriptions (continued) Field Description 1 ADPC1 ADC Pin Control 1 — ADPC1 is used to control the pin associated with channel AD1. 0 AD1 pin I/O control enabled 1 AD1 pin I/O control disabled 0 ADPC0 ADC Pin Control 0 — ADPC0 is used to control the pin associated with channel AD0. 0 AD0 pin I/O control enabled 1 AD0 pin I/O control disabled 14.4.
Chapter 14 Analog-to-Digital Converter (S08ADC10V1) Table 14-10. APCTL2 Register Field Descriptions (continued) Field Description 1 ADPC9 ADC Pin Control 9 — ADPC9 is used to control the pin associated with channel AD9. 0 AD9 pin I/O control enabled 1 AD9 pin I/O control disabled 0 ADPC8 ADC Pin Control 8 — ADPC8 is used to control the pin associated with channel AD8. 0 AD8 pin I/O control enabled 1 AD8 pin I/O control disabled 14.4.
Chapter 14 Analog-to-Digital Converter (S08ADC10V1) Table 14-11. APCTL3 Register Field Descriptions (continued) Field Description 1 ADPC17 ADC Pin Control 17 — ADPC17 is used to control the pin associated with channel AD17. 0 AD17 pin I/O control enabled 1 AD17 pin I/O control disabled 0 ADPC16 ADC Pin Control 16 — ADPC16 is used to control the pin associated with channel AD16. 0 AD16 pin I/O control enabled 1 AD16 pin I/O control disabled 14.
Chapter 14 Analog-to-Digital Converter (S08ADC10V1) are too fast, then the clock must be divided to the appropriate frequency. This divider is specified by the ADIV bits and can be divide-by 1, 2, 4, or 8. 14.5.2 Input Select and Pin Control The pin control registers (APCTL3, APCTL2, and APCTL1) are used to disable the I/O port control of the pins used as analog inputs.
Chapter 14 Analog-to-Digital Converter (S08ADC10V1) 14.5.4.2 Completing Conversions A conversion is completed when the result of the conversion is transferred into the data result registers, ADC1RH and ADC1RL. This is indicated by the setting of COCO. An interrupt is generated if AIEN is high at the time that COCO is set.
Chapter 14 Analog-to-Digital Converter (S08ADC10V1) result of the conversion is transferred to ADC1RH and ADC1RL upon completion of the conversion algorithm. If the bus frequency is less than the fADCK frequency, precise sample time for continuous conversions cannot be guaranteed when short sample is enabled (ADLSMP=0). If the bus frequency is less than 1/11th of the fADCK frequency, precise sample time for continuous conversions cannot be guaranteed when long sample is enabled (ADLSMP=1).
Chapter 14 Analog-to-Digital Converter (S08ADC10V1) 14.5.5 Automatic Compare Function The compare function can be configured to check for either an upper limit or lower limit. After the input is sampled and converted, the result is added to the two’s complement of the compare value (ADC1CVH and ADC1CVL). When comparing to an upper limit (ACFGT = 1), if the result is greater-than or equal-to the compare value, COCO is set.
Chapter 14 Analog-to-Digital Converter (S08ADC10V1) 14.5.7.2 Stop3 Mode With ADACK Enabled If ADACK is selected as the conversion clock, the ADC continues operation during stop3 mode. For guaranteed ADC operation, the MCU’s voltage regulator must remain active during stop3 mode. Consult the module introduction for configuration information for this MCU. If a conversion is in progress when the MCU enters stop3 mode, it continues until completion.
Chapter 14 Analog-to-Digital Converter (S08ADC10V1) 2. Update status and control register 2 (ADCSC2) to select the conversion trigger (hardware or software) and compare function options, if enabled. 3. Update status and control register 1 (ADCSC1) to select whether conversions will be continuous or completed only once, and to enable or disable conversion complete interrupts. The input channel on which conversions will be performed is also selected here. 14.6.1.
Chapter 14 Analog-to-Digital Converter (S08ADC10V1) RESET INITIALIZE ADC ADCCFG = $98 ADCSC2 = $00 ADCSC1 = $41 CHECK COCO=1? NO YES READ ADCRH THEN ADCRL TO CLEAR COCO BIT CONTINUE Figure 14-14. Initialization Flowchart for Example 14.7 Application Information This section contains information for using the ADC module in applications. The ADC has been designed to be integrated into a microcontroller for use in embedded control applications requiring an A/D converter. 14.7.
Chapter 14 Analog-to-Digital Converter (S08ADC10V1) In cases where separate power supplies are used for analog and digital power, the ground connection between these supplies must be at the VSSAD pin. This should be the only ground connection between these supplies if possible. The VSSAD pin makes a good single point ground location. 14.7.1.2 Analog Reference Pins In addition to the analog supplies, the ADC module has connections for two reference voltage inputs.
Chapter 14 Analog-to-Digital Converter (S08ADC10V1) 14.7.2 Sources of Error Several sources of error exist for A/D conversions. These are discussed in the following sections. 14.7.2.1 Sampling Error For proper conversions, the input must be sampled long enough to achieve the proper accuracy. Given the maximum input resistance of approximately 7kΩ and input capacitance of approximately 5.5 pF, sampling to within 1/4LSB (at 10-bit resolution) can be achieved within the minimum sample window (3.
Chapter 14 Analog-to-Digital Converter (S08ADC10V1) • • Average the result by converting the analog input many times in succession and dividing the sum of the results. Four samples are required to eliminate the effect of a 1LSB, one-time error. Reduce the effect of synchronous noise by operating off the asynchronous clock (ADACK) and averaging. Noise that is synchronous to ADCK cannot be averaged out. 14.7.2.
Chapter 14 Analog-to-Digital Converter (S08ADC10V1) converter yields the lower code (and vice-versa). However, even very small amounts of system noise can cause the converter to be indeterminate (between two codes) for a range of input voltages around the transition voltage. This range is normally around 1/2LSB and will increase with noise. This error may be reduced by repeatedly sampling the input and averaging the result. Additionally the techniques discussed in Section 14.7.2.3 will reduce this error.
Chapter 14 Analog-to-Digital Converter (S08ADC10V1) MC9S08AW60 Data Sheet, Rev 2 260 Freescale Semiconductor
Chapter 15 Development Support 15.1 Introduction Development support systems in the HCS08 include the background debug controller (BDC) and the on-chip debug module (DBG). The BDC provides a single-wire debug interface to the target MCU that provides a convenient interface for programming the on-chip FLASH and other nonvolatile memories.
Chapter 15 Development Support 15.1.
Chapter 15 Development Support • Non-intrusive commands can be executed at any time even while the user’s program is running. Non-intrusive commands allow a user to read or write MCU memory locations or access status and control registers within the background debug controller. Typically, a relatively simple interface pod is used to translate commands from a host computer into commands for the custom serial interface to the single-wire background debug system.
Chapter 15 Development Support When no debugger pod is connected to the 6-pin BDM interface connector, the internal pullup on BKGD chooses normal operating mode. When a debug pod is connected to BKGD it is possible to force the MCU into active background mode after reset. The specific conditions for forcing active background depend upon the HCS08 derivative (refer to the introduction to this Development Support section).
Chapter 15 Development Support Figure 15-2 shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target HCS08 MCU. The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target senses the bit level on the BKGD pin.
Chapter 15 Development Support Figure 15-3 shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long enough for the target to recognize it (at least two target BDC cycles).
Chapter 15 Development Support Figure 15-4 shows the host receiving a logic 0 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the target HCS08 finishes it.
Chapter 15 Development Support 15.2.3 BDC Commands BDC commands are sent serially from a host computer to the BKGD pin of the target HCS08 MCU. All commands and data are sent MSB-first using a custom BDC communications protocol. Active background mode commands require that the target MCU is currently in the active background mode while non-intrusive commands may be issued at any time whether the target MCU is in active background mode or running a user application program.
Chapter 15 Development Support Table 15-1. BDC Command Summary Command Mnemonic 1 Active BDM/ Non-intrusive Coding Structure Description SYNC Non-intrusive n/a1 Request a timed reference pulse to determine target BDC communication speed ACK_ENABLE Non-intrusive D5/d Enable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D. ACK_DISABLE Non-intrusive D6/d Disable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D.
Chapter 15 Development Support The SYNC command is unlike other BDC commands because the host does not necessarily know the correct communications speed to use for BDC communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host: • Drives the BKGD pin low for at least 128 cycles of the slowest possible BDC clock (The slowest clock is normally the reference oscillator/64 or the self-clocked rate/64.
Chapter 15 Development Support 15.3 On-Chip Debug System (DBG) Because HCS08 devices do not have external address and data buses, the most important functions of an in-circuit emulator have been built onto the chip with the MCU. The debug system consists of an 8-stage FIFO that can store address or data bus information, and a flexible trigger system to decide when to capture bus information and what information to capture.
Chapter 15 Development Support the host must perform ((8 – CNT) – 1) dummy reads of the FIFO to advance it to the first significant entry in the FIFO. In most trigger modes, the information stored in the FIFO consists of 16-bit change-of-flow addresses. In these cases, read DBGFH then DBGFL to get one coherent word of information out of the FIFO. Reading DBGFL (the low-order byte of the FIFO data port) causes the FIFO to shift so the next word of information is available at the FIFO data port.
Chapter 15 Development Support A force-type breakpoint waits for the current instruction to finish and then acts upon the breakpoint request. The usual action in response to a breakpoint is to go to active background mode rather than continuing to the next instruction in the user application program. The tag vs. force terminology is used in two contexts within the debug module. The first context refers to breakpoint requests from the debug module to the CPU.
Chapter 15 Development Support A-Only — Trigger when the address matches the value in comparator A A OR B — Trigger when the address matches either the value in comparator A or the value in comparator B A Then B — Trigger when the address matches the value in comparator B but only after the address for another cycle matched the value in comparator A. There can be any number of cycles after the A match and before the B match.
Chapter 15 Development Support 15.3.6 Hardware Breakpoints The BRKEN control bit in the DBGC register may be set to 1 to allow any of the trigger conditions described in Section 15.3.5, “Trigger Modes,” to be used to generate a hardware breakpoint request to the CPU. TAG in DBGC controls whether the breakpoint request will be treated as a tag-type breakpoint or a force-type breakpoint. A tag breakpoint causes the current opcode to be marked as it enters the instruction queue.
Chapter 15 Development Support 15.4.1.1 BDC Status and Control Register (BDCSCR) This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL) but is not accessible to user programs because it is not located in the normal memory map of the MCU. 7 R 6 5 4 3 BKPTEN FTS CLKSW BDMACT ENBDM 2 1 0 WS WSF DVF W Normal Reset 0 0 0 0 0 0 0 0 Reset in Active BDM: 1 1 0 0 1 0 0 0 = Unimplemented or Reserved Figure 15-5.
Chapter 15 Development Support Table 15-2. BDCSCR Register Field Descriptions (continued) Field Description 2 WS Wait or Stop Status — When the target CPU is in wait or stop mode, most BDC commands cannot function. However, the BACKGROUND command can be used to force the target CPU out of wait or stop and into active background mode where all BDC commands work.
Chapter 15 Development Support R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 BDFR1 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved 1 BDFR is writable only through serial background mode debug commands, not from user programs. Figure 15-6. System Background Debug Force Reset Register (SBDFR) Table 15-3.
Chapter 15 Development Support 15.4.3.5 Debug FIFO High Register (DBGFH) This register provides read-only access to the high-order eight bits of the FIFO. Writes to this register have no meaning or effect. In the event-only trigger modes, the FIFO only stores data into the low-order byte of each FIFO word, so this register is not used and will read 0x00. Reading DBGFH does not cause the FIFO to shift to the next word.
Chapter 15 Development Support 15.4.3.7 Debug Control Register (DBGC) This register can be read or written at any time. 7 6 5 4 3 2 1 0 DBGEN ARM TAG BRKEN RWA RWAEN RWB RWBEN 0 0 0 0 0 0 0 0 R W Reset Figure 15-7. Debug Control Register (DBGC) Table 15-4. DBGC Register Field Descriptions Field Description 7 DBGEN Debug Module Enable — Used to enable the debug module. DBGEN cannot be set to 1 if the MCU is secure.
Chapter 15 Development Support 15.4.3.8 Debug Trigger Register (DBGT) This register can be read any time, but may be written only if ARM = 0, except bits 4 and 5 are hard-wired to 0s. 7 6 TRGSEL BEGIN 0 0 R 5 4 0 0 3 2 1 0 TRG3 TRG2 TRG1 TRG0 0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 15-8. Debug Trigger Register (DBGT) Table 15-5.
Chapter 15 Development Support 15.4.3.9 Debug Status Register (DBGS) This is a read-only status register. R 7 6 5 4 3 2 1 0 AF BF ARMF 0 CNT3 CNT2 CNT1 CNT0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 15-9. Debug Status Register (DBGS) Table 15-6. DBGS Register Field Descriptions Field Description 7 AF Trigger Match A Flag — AF is cleared at the start of a debug run and indicates whether a trigger match A condition was met since arming.
Appendix A Electrical Characteristics and Timing Specifications A.1 Introduction This section contains electrical and timing specifications. A.2 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give you a better understanding, the following classification is used and the parameters are tagged accordingly in the tables where appropriate: Table A-1.
Appendix A Electrical Characteristics and Timing Specifications Table A-2. Absolute Maximum Ratings Rating Symbol Value Unit Supply voltage VDD –0.3 to + 5.8 V Input voltage VIn – 0.3 to VDD + 0.3 V Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 ID ± 25 mA Maximum current into VDD IDD 120 mA Storage temperature Tstg –55 to +150 °C TJ 150 °C Maximum junction temperature 1 Input must be current limited to the value specified.
Appendix A Electrical Characteristics and Timing Specifications A.4 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and it is user-determined rather than being controlled by the MCU design.
Appendix A Electrical Characteristics and Timing Specifications Solving equations 1 and 2 for K gives: K = PD × (TA + 273°C) + θJA × (PD)2 Eqn. A-3 where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations 1 and 2 iteratively for any value of TA. A.
Appendix A Electrical Characteristics and Timing Specifications A.6 DC Characteristics This section includes information about power supply requirements, I/O pin characteristics, and power supply current in various operating modes. Table A-6. MCU Operating Conditions Characteristic Supply Voltage Min Typ Max Uni t 2.7 — 5.5 V –40 –40 -40 — — — 125 105 85 Min Typ1 Max VDD – 1.5 VDD – 1.5 VDD – 0.8 VDD – 0.8 — — — — — — — — °C Temperature M V C Table A-7.
Appendix A Electrical Characteristics and Timing Specifications Table A-7. DC Characteristics (continued) Num C 9 10 Parameter 2 P High Impedance (off-state) leakage current 3 P Internal pullup resistors 4 Symbol Min Typ1 Max Unit |IOZ| — 0.01 1 µA RPU 20 45 65 kΩ 11 P Internal pulldown resistors RPD 20 45 65 kΩ 12 C Input Capacitance; all non-supply pins CIn — — 8 pF 13 P POR rearm voltage VPOR 0.9 1.4 2.
Appendix A Electrical Characteristics and Timing Specifications 8 IRQ does not have a clamp diode to VDD. Do not drive IRQ above VDD. 0.7 0.8 125ºC 85ºC 25ºC 40ºC 0.6 0.7 125ºC 85ºC 25ºC 40ºC IOL = 2mA 0.6 VOL (V) VOL (V) 0.5 0.4 0.3 0.5 0.4 0.2 VDD = 5V 0.1 0.3 0 0.2 0.2 0.6 1.2 1.6 IOL (mA) 2.0 2.4 3.0 2.75 3.0 3.25 3.5 3.75 4.0 4.25 4.5 4.75 5.0 5.25 5.5 VDD (V) Figure A-1. Typical Low-Side Driver (Sink) Characteristics — Low Drive (PTxDSn = 0) 0.9 0.7 VOL (V) 0.
Appendix A Electrical Characteristics and Timing Specifications 1.2 1.4 VDD – VOL (V) VDD – VOL (V) 0.8 125ºC 85ºC 25ºC 40ºC 1.2 125ºC 85ºC 25ºC 40ºC 1.0 0.6 0.4 0.2 1.0 0.8 0.6 0.4 0.2 VDD = 5V 0 IOH = -2mA 0 0.2 0.6 1.2 1.6 IOH (mA) 2.0 2.4 2.75 3.0 3.25 3.5 3.75 4.0 4.25 4.5 4.75 5.0 5.25 5.5 VDD (V) 3.0 Figure A-3. Typical High-Side (Source) Characteristics — Low Drive (PTxDSn = 0) 1.2 1.5 0.8 125ºC 85ºC 25ºC 40ºC 1.3 VDD – VOL (V) VDD – VOL (V) 1.
Appendix A Electrical Characteristics and Timing Specifications A.7 Supply Current Characteristics Table A-8. Supply Current Characteristics Num C Parameter Symbol 2 1 2 3 P P P Run supply current measured at (CPU clock = 2 MHz, fBus = 1 MHz) RIDD Run supply current2 measured at (CPU clock = 16 MHz, fBus = 8 MHz) RIDD Run supply current3 measured at (CPU clock = 40 MHz, fBus = 20 MHz) RIDD VDD (V) Typ1 Max 5 0.750 0.950 3 0.570 0.770 5 4.90 5.10 3 3.50 3.70 5 16.8 18.
IDD (mA) Appendix A Electrical Characteristics and Timing Specifications 24.0 22.0 20.0 18.0 16.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0 20 MHz – FEI Clock Mode, ADC Module Off 20 MHz – FBE Clock Mode, ADC Module Off 8 MHz – FEI Clock Mode, ADC Module Off 8 MHz – FBE Clock Mode, ADC Module Off 1 MHz – FEI Clock Mode, ADC Module Off 1 MHz – FBE Clock Mode, ADC Module Off 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 VDD (V) Note: All modules except ADC active. Figure A-5.
Appendix A Electrical Characteristics and Timing Specifications Stop3 IDD (A) IDD (A) Average of Meas IDD 50.0E–6 45.0E–6 40.0E–6 35.0E–6 30.0E–6 25.0E–6 20.0E–6 15.0E–6 10.0E–6 5.0E–6 000.0E+0 Temp –40 25 85 125 1.8 2 3 2.5 3.5 VDD (V) 4 4.5 5 Figure A-7. Typical Stop3 IDD A.8 ADC Characteristics Table A-9. 5 Volt 10-bit ADC Operating Conditions Symb Min Typ1 Max Unit Absolute VDDAD 2.7 — 5.
Appendix A Electrical Characteristics and Timing Specifications SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT Pad leakage due to input protection ZAS RAS ADC SAR ENGINE RADIN + VADIN VAS CAS + – – RADIN INPUT PIN RADIN INPUT PIN RADIN INPUT PIN CADIN Figure A-8. ADC Input Impedance Equivalency Diagram Table A-10.
Appendix A Electrical Characteristics and Timing Specifications Table A-10. 10-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued) Characteristic Conditions ADC asynchronous clock source tADACK = 1/fADACK High speed (ADLPC = 0) Conversion time (Including sample time) Short sample (ADLSMP = 0) C Symb Min Typ1 Max Unit P fADACK 2 3.3 5 MHzS 1.25 2 3.3 — 20 — — 40 — — 3.5 — — 23.5 — — ±1 ±2.5 — ±0.5 ±1.0 — ±0.5 ±1.0 — ±0.3 ±0.
Appendix A Electrical Characteristics and Timing Specifications A.9 Internal Clock Generation Module Characteristics ICG EXTAL XTAL RS RF C1 Crystal or Resonator C2 Table A-11.
Appendix A Electrical Characteristics and Timing Specifications A.9.1 ICG Frequency Specifications Table A-12.
Appendix A Electrical Characteristics and Timing Specifications Table A-12. ICG Frequency Specifications (continued) (VDDA = VDDA (min) to VDDA (max), Temperature Range = –40 to 125°C Ambient) Num C Characteristic Symbol Min Typ1 Max Unit — ±0.5 ±2 % — ±0.5 ±2 % MC9S08AWxx: Internal oscillator deviation from trimmed frequency9 19 1 2 3 4 5 6 7 8 9 C VDD = 2.7 – 5.5 V, (constant temperature) P VDD = 5.
Appendix A Electrical Characteristics and Timing Specifications Internal Oscillator Deviation from Trimmed Frequency Variable 5V 3V 0.0 Percent (%) –0.5 –1.0 –1.5 –2.0 –50 –25 0 25 50 Temp 75 100 125 Device trimmed at 25°C at 3.0 V. Figure A-9.
Appendix A Electrical Characteristics and Timing Specifications A.10 AC Characteristics This section describes ac timing characteristics for each peripheral system. For detailed information about how clocks for the bus are generated, see Chapter 8, “Internal Clock Generator (S08ICGV4).” A.10.1 Control Timing Table A-13.
Period ( sec) Appendix A Electrical Characteristics and Timing Specifications 1300 1250 1200 1150 1100 1050 1000 950 900 850 800 +3 SD Mean –3 SD –20 –40 0 20 40 60 Temperature (ºC) 80 100 120 Figure A-10. Typical RTI Clock Period vs. Temperature textrst RESET PIN Figure A-11. Reset Timing BKGD/MS RESET tMSH tMSSU Figure A-12. Active Background Debug Mode Latch Timing tIHIL IRQ/KBIP7-KBIP4 IRQ/KBIPx tILIH Figure A-13.
Appendix A Electrical Characteristics and Timing Specifications A.10.2 Timer/PWM (TPM) Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table A-14.
Appendix A Electrical Characteristics and Timing Specifications A.11 SPI Characteristics Table A-15 and Figure A-16 through Figure A-19 describe the timing requirements for the SPI system. Table A-15.
Appendix A Electrical Characteristics and Timing Specifications SS1 (OUTPUT) 1 2 SCK (CPOL = 0) (OUTPUT) 3 5 4 SCK (CPOL = 1) (OUTPUT) 5 4 6 MISO (INPUT) 7 MSB IN2 BIT 6 . . . 1 10 MOSI (OUTPUT) LSB IN 10 MSB OUT2 11 BIT 6 . . . 1 LSB OUT NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure A-16.
Appendix A Electrical Characteristics and Timing Specifications SS (INPUT) 3 1 SCK (CPOL = 0) (INPUT) 5 4 2 SCK (CPOL = 1) (INPUT) 5 4 8 MISO (OUTPUT) 11 10 BIT 6 . . . 1 MSB OUT SLAVE SLAVE LSB OUT SEE NOTE 7 6 MOSI (INPUT) 9 BIT 6 . . . 1 MSB IN LSB IN NOTE: 1. Not defined but normally MSB of character just received Figure A-18.
Appendix A Electrical Characteristics and Timing Specifications A.12 FLASH Specifications This section provides details about program/erase times and program-erase endurance for the FLASH memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see Chapter 4, “Memory.” Table A-16.
Appendix A Electrical Characteristics and Timing Specifications A.13 EMC Performance Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance.
Appendix A Electrical Characteristics and Timing Specifications The conducted susceptibility is determined by injecting the transient susceptibility signal on each pin of the microcontroller. The transient waveform and injection methodology is based on IEC 61000-4-4 (EFT/B). The transient voltage required to cause performance degradation on any pin in the tested configuration is greater than or equal to the reported levels unless otherwise indicated by footnotes below the table. Table A-18.
Appendix B Ordering Information and Mechanical Drawings B.1 Ordering Information This section contains ordering numbers for MC9S08AW60 Series devices. See below for an example of the device numbering system. Table B-1.
Appendix B Ordering Information and Mechanical Drawings B.2 B.2.1 Orderable Part Numbering System Consumer and Industrial Orderable Part Numbering System MC 9 S08 AW 60 C XX E Pb free indicator Package designator (See Table B-3) Status (MC =Consumer & Industrial Fully Qualified) Memory (9 = FLASH-based) Core Family B.2.
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