Datasheet

Chapter 6 Parallel Input/Output
MC9S08AW60 Data Sheet, Rev 2
Freescale Semiconductor 101
6.7.10 Port E Pin Control Registers (PTEPE, PTESE, PTEDS)
In addition to the I/O control, port E pins are controlled by the registers listed below.
76543210
R
PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0
W
Reset 00000000
Figure 6-31. Internal Pullup Enable for Port E (PTEPE)
Table 6-24. PTEPE Register Field Descriptions
Field Description
7:0
PTEPE[7:0]
Internal Pullup Enable for Port E Bits— Each of these control bits determines if the internal pullup device is
enabled for the associated PTE pin. For port E pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port E bit n.
1 Internal pullup device enabled for port E bit n.
76543210
R
PTESE7 PTESE6 PTESE5 PTESE4 PTESE3 PTESE2 PTESE1 PTESE0
W
Reset 00000000
Figure 6-32. Output Slew Rate Control Enable for Port E (PTESE)
Table 6-25. PTESE Register Field Descriptions
Field Description
7:0
PTESE[7:0]
Output Slew Rate Control Enable for Port E Bits — Each of these control bits determine whether output slew
rate control is enabled for the associated PTE pin. For port E pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port E bit n.
1 Output slew rate control enabled for port E bit n.