Datasheet

Chapter 6 Parallel Input/Output
MC9S08AW60 Data Sheet, Rev 2
Freescale Semiconductor 107
6.7.14 Port G Pin Control Registers (PTGPE, PTGSE, PTGDS)
In addition to the I/O control, port G pins are controlled by the registers listed below.
76543210
R
PTGPE6 PTGPE5 PTGPE4 PTGPE3 PTGPE2 PTGPE1 PTGPE0
W
Reset 00000000
Figure 6-41. Internal Pullup Enable for Port G Bits (PTGPE)
Table 6-34. PTGPE Register Field Descriptions
Field Description
6:0
PTGPE[6:0]
Internal Pullup Enable for Port G Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTG pin. For port G pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port G bit n.
1 Internal pullup device enabled for port G bit n.
76543210
R
PTGSE6 PTGSE5 PTGSE4 PTGSE3 PTGSE2 PTGSE1 PTGSE0
W
Reset 00000000
Figure 6-42. Output Slew Rate Control Enable for Port G Bits (PTGSE)
Table 6-35. PTGSE Register Field Descriptions
Field Description
6:0
PTGSE[6:0]
Output Slew Rate Control Enable for Port G Bits— Each of these control bits determine whether output slew
rate control is enabled for the associated PTG pin. For port G pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port G bit n.
1 Output slew rate control enabled for port G bit n.