Datasheet

Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08AW60 Data Sheet, Rev 2
120 Freescale Semiconductor
IX = 16-bit indexed no offset
IX+ = 16-bit indexed no offset, post increment (CBEQ and MOV only)
IX1 = 16-bit indexed with 8-bit offset from H:X
IX1+ = 16-bit indexed with 8-bit offset, post increment
(CBEQ only)
IX2 = 16-bit indexed with 16-bit offset from H:X
REL = 8-bit relative offset
SP1 = Stack pointer with 8-bit offset
SP2 = Stack pointer with 16-bit offset
Table 7-2. HCS08 Instruction Set Summary (Sheet 1 of 7)
Source
Form
Operation Description
Effect
on CCR
Address
Mode
Opcode
Operand
Bus Cycles
1
VH I NZC
ADC #opr8i
ADC opr8a
ADC opr16a
ADC oprx16,X
ADC oprx8,X
ADC ,X
ADC oprx16,SP
ADC oprx8,SP
Add with Carry A ← (A) + (M) + (C) ↕↕
–
↕↕↕
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A9
B9
C9
D9
E9
F9
9ED9
9EE9
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
ADD #opr8i
ADD opr8a
ADD opr16a
ADD oprx16,X
ADD oprx8,X
ADD ,X
ADD oprx16,SP
ADD oprx8,SP
Add without Carry A ← (A) + (M) ↕↕– ↕↕↕
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
AB
BB
CB
DB
EB
FB
9EDB
9EEB
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
AIS #opr8i
Add Immediate Value
(Signed) to Stack Pointer
SP ← (SP) + (M)
M is sign extended to a 16-bit value
– – – – – – IMM A7 ii 2
AIX #opr8i
Add Immediate Value
(Signed) to Index
Register (H:X)
H:X ← (H:X) + (M)
M is sign extended to a 16-bit value
– – – – – – IMM AF ii 2
AND #opr8i
AND opr8a
AND opr16a
AND oprx16,X
AND oprx8,X
AND ,X
AND oprx16,SP
AND oprx8,SP
Logical AND A ← (A) & (M) 0 – – ↕↕–
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A4
B4
C4
D4
E4
F4
9ED4
9EE4
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
ASL opr8a
ASLA
ASLX
ASL oprx8,X
ASL ,X
ASL oprx8,SP
Arithmetic Shift Left
(Same as LSL)
↕ ––↕↕↕
DIR
INH
INH
IX1
IX
SP1
38
48
58
68
78
9E68
dd
ff
ff
5
1
1
5
4
6
ASR opr8a
ASRA
ASRX
ASR oprx8,X
ASR ,X
ASR oprx8,SP
Arithmetic Shift Right ↕ ––↕↕↕
DIR
INH
INH
IX1
IX
SP1
37
47
57
67
77
9E67
dd
ff
ff
5
1
1
5
4
6
BCC rel Branch if Carry Bit Clear Branch if (C) = 0 – – – – – – REL 24 rr 3
C
b0
b7
0
b0
b7
C