Datasheet

Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08AW60 Data Sheet, Rev 2
126 Freescale Semiconductor
TAP
Transfer Accumulator to
CCR
CCR ← (A) ↕↕↕↕↕↕INH 84 1
TAX
Transfer Accumulator to
X (Index Register Low)
X ← (A)
––––––
INH 97 1
TPA
Transfer CCR to
Accumulator
A ← (CCR)
––––––
INH 85 1
TST opr8a
TSTA
TSTX
TST oprx8,X
TST ,X
TST oprx8,SP
Test for Negative or Zero
(M) – 0x00
(A) – 0x00
(X) – 0x00
(M) – 0x00
(M) – 0x00
(M) – 0x00
0––
↕↕
–
DIR
INH
INH
IX1
IX
SP1
3D
4D
5D
6D
7D
9E6D
dd
ff
ff
4
1
1
4
3
5
TSX Transfer SP to Index Reg. H:X ← (SP) + 0x0001
––––––
INH 95 2
TXA
Transfer X (Index Reg.
Low) to Accumulator
A ← (X)
––––––
INH 9F 1
TXS Transfer Index Reg. to SP SP ← (H:X) – 0x0001
––––––
INH 94 2
WAIT
Enable Interrupts; Wait
for Interrupt
I bit ← 0; Halt CPU
––0–––
INH 8F 2+
1
Bus clock frequency is one-half of the CPU clock frequency.
Table 7-2. HCS08 Instruction Set Summary (Sheet 7 of 7)
Source
Form
Operation Description
Effect
on CCR
Address
Mode
Opcode
Operand
Bus Cycles
1
VH I NZC