Datasheet

Chapter 8 Internal Clock Generator (S08ICGV4)
MC9S08AW60 Data Sheet, Rev 2
142 Freescale Semiconductor
entering off mode. If CLKS bits are set to 01 or 11 coming out of the Off state, the ICG enters this mode
until ICGDCLK is stable as determined by the DCOS bit. After ICGDCLK is considered stable, the ICG
automatically closes the loop by switching to FLL engaged (internal or external) as selected by the CLKS
bits.
Figure 8-13. Detailed Frequency-Locked Loop Block Diagram
8.4.3 FLL Engaged, Internal Clock (FEI) Mode
FLL engaged internal (FEI) is entered when any of the following conditions occur:
• CLKS bits are written to 01
• The DCO clock stabilizes (DCOS = 1) while in SCM upon exiting the off state with CLKS = 01
In FLL engaged internal mode, the reference clock is derived from the internal reference clock
ICGIRCLK, and the FLL loop will attempt to lock the ICGDCLK frequency to the desired value, as
selected by the MFD bits.
REFERENCE
DIVIDER (/7)
SUBTRACTOR
LOOP
FILTER
DIGITALLY
CONTROLLED
OSCILLATOR
CLOCK
ICGOUT
ICG2DCLK
RESET AND
INTERRUPT
IRQ
FLL ANALOG
SELECT
CIRCUIT
PULSE
COUNTER
FREQUENCY-
ICGERCLK
LOCK AND
DETECTOR
CONTROL
RESET
REDUCED
FREQUENCY
DIVIDER (R)
LOSS OF CLOCK
ICGDCLK
LOOP (FLL)
DIGITAL
COUNTER ENABLE
LOCKED
OVERFLOW
1x
2x
ICGIRCLK
CLKST
RANGE
MFD
RANGE
CLKS
RFD
FLT
LOCRE
CLKST
LOLRE
ICGIF
LOCD
ERCS
LOCS
LOLS
LOCKDCOS