Datasheet

Appendix A Electrical Characteristics and Timing Specifications
MC9S08AW60 Data Sheet, Rev 2
286 Freescale Semiconductor
Solving equations 1 and 2 for K gives:
K = P
D
× (T
A
+ 273°C) + θ
JA
× (P
D
)
2
Eqn. A-3
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring
P
D
(at equilibrium) for a known T
A
. Using this value of K, the values of P
D
and T
J
can be obtained by
solving equations 1 and 2 iteratively for any value of T
A
.
A.5 ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM), the Machine Model (MM) and the Charge Device Model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Table A-4. ESD and Latch-up Test Conditions
Model Description Symbol Value Unit
Human Body
Model
Series Resistance R1 1500
Ω
Storage Capacitance C 100 pF
Number of Pulse per pin 3
Machine Model
Series Resistance R1 0
Ω
Storage Capacitance C 200 pF
Number of Pulse per pin 3
Latch-Up
Minimum input voltage limit –2.5 V
Maximum input voltage limit 7.5 V
Table A-5. ESD and Latch-Up Protection Characteristics
Num C Rating Symbol Min Max Unit
1 C Human Body Model (HBM)
V
HBM
± 2000 V
2 C Machine Model (MM)
V
MM
± 200 V
3 C Charge Device Model (CDM)
V
CDM
± 500 V
4C
Latch-up Current at T
A
= 125°CI
LAT
± 100 mA