Datasheet

Appendix A Electrical Characteristics and Timing Specifications
MC9S08AW60 Data Sheet, Rev 2
Freescale Semiconductor 303
A.11 SPI Characteristics
Table A-15 and Figure A-16 through Figure A-19 describe the timing requirements for the SPI system.
Table A-15. SPI Electrical Characteristic
Num
1
1
Refer to Figure A-16 through Figure A-19.
C Characteristic
2
2
All timing is shown with respect to 20% V
DD
and 70% V
DD
, unless noted; 100 pF load on all SPI
pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output
pins.
Symbol Min Max Unit
Operating frequency
3
Master
Slave
3
Maximum baud rate must be limited to 5 MHz due to pad input characteristics.
f
op
f
op
f
Bus
/2048
dc
f
Bus
/2
f
Bus
/4
Hz
1 Cycle time
Master
Slave
t
SCK
t
SCK
2
4
2048
—
t
cyc
t
cyc
2 Enable lead time
Master
Slave
t
Lead
t
Lead
—
1/2
1/2
—
t
SCK
t
SCK
3 Enable lag time
Master
Slave
t
Lag
t
Lag
—
1/2
1/2
—
t
SCK
t
SCK
4 Clock (SPSCK) high time
Master and Slave
t
SCKH
1/2 t
SCK
– 25 — ns
5 Clock (SPSCK) low time Master
and Slave
t
SCKL
1/2 t
SCK
– 25 — ns
6 Data setup time (inputs)
Master
Slave
t
SI(M)
t
SI(S)
30
30
—
—
ns
ns
7 Data hold time (inputs)
Master
Slave
t
HI(M)
t
HI(S)
30
30
—
—
ns
ns
8 Access time, slave
4
4
Time to data active from high-impedance state.
t
A
040ns
9 Disable time, slave
5
5
Hold time to high-impedance state.
t
dis
—40ns
10 Data setup time (outputs)
Master
Slave
t
SO
t
SO
25
25
—
—
ns
ns
11 Data hold time (outputs)
Master
Slave
t
HO
t
HO
–10
–10
—
—
ns
ns