Datasheet

Chapter 5 Resets, Interrupts, and System Configuration
MC9S08AW60 Data Sheet, Rev 2
74 Freescale Semiconductor
5.9.2 System Reset Status Register (SRS)
This register includes seven read-only status flags to indicate the source of the most recent reset. When a
debug host forces reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS will be
set. Writing any value to this register address clears the COP watchdog timer without affecting the contents
of this register. The reset state of these bits depends on what caused the MCU to reset.
Figure 5-3. System Reset Status (SRS)
76543210
R POR PIN COP ILOP 0 ICG LVD 0
W Writing any value to SIMRS address clears COP watchdog timer.
POR10000010
LVR:
U0000010
Any other
reset:
0
(1)
1
Any of these reset sources that are active at the time of reset will cause the corresponding bit(s) to be set; bits corresponding
to sources that are not active at the time of reset will be cleared.
(1) (1)
0
(1)
00
U = Unaffected by reset
Table 5-3. SRS Register Field Descriptions
Field Description
7
POR
Power-On Reset — Reset was caused by the power-on detection logic. Because the internal supply voltage was
ramping up at the time, the low-voltage reset (LVR) status bit is also set to indicate that the reset occurred while
the internal supply was below the LVR threshold.
0 Reset not caused by POR.
1 POR caused reset.
6
PIN
External Reset Pin — Reset was caused by an active-low level on the external reset pin.
0 Reset not caused by external reset pin.
1 Reset came from external reset pin.
5
COP
Computer Operating Properly (COP) Watchdog — Reset was caused by the COP watchdog timer timing out.
This reset source may be blocked by COPE = 0.
0 Reset not caused by COP timeout.
1 Reset caused by COP timeout.
4
ILOP
Illegal Opcode — Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP
instruction is considered illegal if stop is disabled by STOPE = 0 in the SOPT register. The BGND instruction is
considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register.
0 Reset not caused by an illegal opcode.
1 Reset caused by an illegal opcode.