Datasheet

Chapter 5 Resets, Interrupts, and System Configuration
MC9S08AW60 Data Sheet, Rev 2
76 Freescale Semiconductor
5.9.5 System MCLK Control Register (SMCLK)
This register is used to control the MCLK clock output.
MCLK frequency = Bus Clock frequency ÷ (2 * MCSEL) Eqn. 5-1
76543210
R
COPE COPT STOPE
00
W
Reset 11010011
= Unimplemented or Reserved
Figure 5-5. System Options Register (SOPT)
Table 5-5. SOPT Register Field Descriptions
Field Description
7
COPE
COP Watchdog Enable — This write-once bit defaults to 1 after reset.
0 COP watchdog timer disabled.
1 COP watchdog timer enabled (force reset on timeout).
6
COPT
COP Watchdog Timeout — This write-once bit defaults to 1 after reset.
0 Short timeout period selected (2
13
cycles of BUSCLK).
1 Long timeout period selected (2
18
cycles of BUSCLK).
5
STOPE
Stop Mode Enable — This write-once bit defaults to 0 after reset, which disables stop mode. If stop mode is
disabled and a user program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.
1 Stop mode enabled.
76543210
R000
MPE
0
MCSEL
W
Reset 00000000
= Unimplemented or Reserved
Figure 5-6. System MCLK Control Register (SMCLK)
Table 5-6. SMCLK Register Field Descriptions
Field Description
4
MPE
MCLK Pin Enable — This bit is used to enable the MCLK function.
0 MCLK output disabled.
1 MCLK output enabled on PTC2 pin.
2:0
MCSEL
MCLK Divide Select — These bits are used to select the divide ratio for the MCLK output according to the
formula below when the MCSEL bits are not equal to all zeroes. In the case that the MCSEL bits are all zero and
MPE is set, the pin is driven low. See Equation 5-1.