Datasheet

Chapter 5 Resets, Interrupts, and System Configuration
MC9S08AW60 Data Sheet, Rev 2
Freescale Semiconductor 79
5.9.8 System Power Management Status and Control 1 Register (SPMSC1)
Figure 5-10. System Power Management Status and Control 1 Register (SPMSC1)
7654321
1
1
Bit 1 is a reserved bit that must always be written to 0.
0
R LVDF 0
LVDIE LVDRE
(2)
2
This bit can be written only one time after reset. Additional writes are ignored.
LVDSE
(2)
LVDE
(2)
BGBE
W LVDACK
Reset 00011100
= Unimplemented or Reserved
Table 5-11. SPMSC1 Register Field Descriptions
Field Description
7
LVDF
Low-Voltage Detect Flag — Provided LVDE = 1, this read-only status bit indicates a low-voltage detect event.
6
LVDACK
Low-Voltage Detect Acknowledge — This write-only bit is used to acknowledge low voltage detection errors
(write 1 to clear LVDF). Reads always return 0.
5
LVDIE
Low-Voltage Detect Interrupt Enable — This read/write bit enables hardware interrupt requests for LVDF.
0 Hardware interrupt disabled (use polling).
1 Request a hardware interrupt when LVDF = 1.
4
LVDRE
Low-Voltage Detect Reset Enable — This read/write bit enables LVDF events to generate a hardware reset
(provided LVDE = 1).
0 LVDF does not generate hardware resets.
1 Force an MCU reset when LVDF = 1.
3
LVDSE
Low-Voltage Detect Stop Enable — Provided LVDE = 1, this read/write bit determines whether the low-voltage
detect function operates when the MCU is in stop mode.
0 Low-voltage detect disabled during stop mode.
1 Low-voltage detect enabled during stop mode.
2
LVDE
Low-Voltage Detect Enable — This read/write bit enables low-voltage detect logic and qualifies the operation
of other bits in this register.
0 LVD logic disabled.
1 LVD logic enabled.
0
BGBE
Bandgap Buffer Enable — The BGBE bit is used to enable an internal buffer for the bandgap voltage reference
for use by the ADC module on one of its internal channels.
0 Bandgap buffer disabled.
1 Bandgap buffer enabled.