Datasheet

Chapter 5 Resets, Interrupts, and System Configuration
MC9S08AW60 Data Sheet, Rev 2
80 Freescale Semiconductor
5.9.9 System Power Management Status and Control 2 Register (SPMSC2)
This register is used to report the status of the low voltage warning function, and to configure the stop mode
behavior of the MCU.
Figure 5-11. System Power Management Status and Control 2 Register (SPMSC2)
76543210
R LVWF 0
LVDV LVWV
PPDF 0
PPDC
1
1
This bit can be written only one time after reset. Additional writes are ignored.
W
LVWACK PPDACK
Power-on
reset:
0
(2)
2
LVWF will be set in the case when V
Supply
transitions below the trip point or after reset and V
Supply
is already below V
LVW
.
0000000
LVD
reset:
0
(2)
0UU0000
Any other
reset:
0
(2)
0UU0000
= Unimplemented or Reserved U = Unaffected by reset
Table 5-12. SPMSC2 Register Field Descriptions
Field Description
7
LVWF
Low-Voltage Warning Flag — The LVWF bit indicates the low voltage warning status.
0 Low voltage warning not present.
1 Low voltage warning is present or was present.
6
LVWACK
Low-Voltage Warning Acknowledge — The LVWACK bit is the low-voltage warning acknowledge.
Writing a 1 to LVWACK clears LVWF to a 0 if a low voltage warning is not present.
5
LVDV
Low-Voltage Detect Voltage Select — The LVDV bit selects the LVD trip point voltage (V
LVD
).
0 Low trip point selected (V
LVD
= V
LVDL
).
1 High trip point selected (V
LVD
= V
LVDH
).
4
LVWV
Low-Voltage Warning Voltage Select — The LVWV bit selects the LVW trip point voltage (V
LVW
).
0 Low trip point selected (V
LVW
= V
LVWL
).
1 High trip point selected (V
LVW
= V
LVWH
).
3
PPDF
Partial Power Down Flag — The PPDF bit indicates that the MCU has exited the stop2 mode.
0 Not stop2 mode recovery.
1 Stop2 mode recovery.
2
PPDACK
Partial Power Down Acknowledge — Writing a 1 to PPDACK clears the PPDF bit.
0
PPDC
Partial Power Down Control — The write-once PPDC bit controls whether stop2 or stop3 mode is selected.
0 Stop3 mode enabled.
1 Stop2, partial power down, mode enabled.