Datasheet

Chapter 6 Parallel Input/Output
MC9S08AW60 Data Sheet, Rev 2
98 Freescale Semiconductor
6.7.8 Port D Pin Control Registers (PTDPE, PTDSE, PTDDS)
In addition to the I/O control, port D pins are controlled by the registers listed below.
76543210
R
PTDPE7 PTDPE6 PTDPE5 PTDPE4 PTDPE3 PTDPE2 PTDPE1 PTDPE0
W
Reset 00000000
Figure 6-26. Internal Pullup Enable for Port D (PTDPE)
Table 6-19. PTDPE Register Field Descriptions
Field Description
7:0
PTDPE[7:0]
Internal Pullup Enable for Port D Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTD pin. For port D pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port D bit n.
1 Internal pullup device enabled for port D bit n.
76543210
R
PTDSE7 PTDSE6 PTDSE5 PTDSE4 PTDSE3 PTDSE2 PTDSE1 PTDSE0
W
Reset 00000000
Figure 6-27. Output Slew Rate Control Enable for Port D (PTDSE)
Table 6-20. PTDSE Register Field Descriptions
Field Description
7:0
PTDSE[7:0]
Output Slew Rate Control Enable for Port D Bits — Each of these control bits determine whether output slew
rate control is enabled for the associated PTD pin. For port D pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port D bit n.
1 Output slew rate control enabled for port D bit n.