MC9S08DZ128 MC9S08DZ96 MC9S08DV128 MC9S08DV96 Data Sheet HCS08 Microcontrollers MC9S08DZ128 Rev. 1 5/2008 freescale.
MC9S08DZ128 Series Features 8-Bit HCS08 Central Processor Unit (CPU) • 40-MHz HCS08 CPU (20-MHz bus) • HC08 instruction set with added BGND instruction • Support for up to 32 interrupt/reset sources On-Chip Memory • FLASH read/program/erase over full operating voltage and temperature • EEPROM in-circuit programmable memory; 8-byte single-page or 4-byte dual-page erase sector; Program and Erase while executing FLASH; Erase abort • Random-access memory (RAM) MC9S08 DZ128 MC9S08 DZ96 MC9S08 DV128 MC9S08 DV
MC9S08DZ128 Series Data Sheet Covers: MC9S08DZ128 MC9S08DZ96 MC9S08DV128 MC9S08DV96 MC9S08DZ128 Rev. 1 5/2008 Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2007, 2008. All rights reserved.
Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. Revision Number Revision Date 1 4/2008 Description of Changes Initial Release © Freescale Semiconductor, Inc., 2007, 2008. All rights reserved.
List of Chapters Chapter Title Page Chapter 1 Device Overview .............................................................................. 21 Chapter 2 Pins and Connections ..................................................................... 27 Chapter 3 Modes of Operation ......................................................................... 39 Chapter 4 Memory .............................................................................................
Contents Section Number Title Page Chapter 1 Device Overview 1.1 1.2 1.3 Devices in the MC9S08DZ128 Series..............................................................................................21 MCU Block Diagram .......................................................................................................................23 System Clock Distribution ...............................................................................................................
Section Number 4.5 4.6 Title Page 4.4.3 MMU Registers and Control Bits .....................................................................................63 RAM.................................................................................................................................................66 FLASH and EEPROM .....................................................................................................................67 4.6.1 Features ...............................................
Section Number Title Page Chapter 6 Parallel Input/Output Control 6.1 6.2 6.3 6.4 6.5 Port Data and Data Direction .........................................................................................................101 Pull-up, Slew Rate, and Drive Strength..........................................................................................102 Pin Interrupts ..................................................................................................................................103 6.
Section Number 7.5 7.6 Title Page 7.4.2 Interrupt Sequence ..........................................................................................................149 7.4.3 Wait Mode Operation ......................................................................................................150 7.4.4 Stop Mode Operation ......................................................................................................150 7.4.5 BGND Instruction ....................................................
Section Number 9.3 9.4 Title Page Memory Map .................................................................................................................................203 9.3.1 Register Descriptions ......................................................................................................203 Functional Description ...................................................................................................................
Section Number Title Page 10.6 Application Information .................................................................................................................229 10.6.1 External Pins and Routing ..............................................................................................229 10.6.2 Sources of Error ..............................................................................................................230 Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.1 Introduction ..
Section Number Title Page 12.3 Register Definition .........................................................................................................................257 12.3.1 MSCAN Control Register 0 (CANCTL0) ......................................................................257 12.3.2 MSCAN Control Register 1 (CANCTL1) ......................................................................260 12.3.3 MSCAN Bus Timing Register 0 (CANBTR0) ........................................................
Section Number Title Page 13.2 External Signal Description ...........................................................................................................312 13.2.1 SPSCK — SPI Serial Clock ............................................................................................312 13.2.2 MOSI — Master Data Out, Slave Data In ......................................................................312 13.2.3 MISO — Master Data In, Slave Data Out ...............................................
Section Number Title Page Chapter 15 Real-Time Counter (S08RTCV1) 15.1 Introduction ....................................................................................................................................343 15.1.1 RTC Clock Signal Names ...............................................................................................343 15.1.2 Features ...........................................................................................................................345 15.1.
Section Number Title Page Chapter 17 Development Support 17.1 Introduction ....................................................................................................................................379 17.1.1 Forcing Active Background ............................................................................................379 17.1.2 Features ...........................................................................................................................380 17.
Section Number Title Page A.5 A.6 A.7 A.8 A.9 A.10 A.11 A.12 ESD Protection and Latch-Up Immunity ......................................................................................422 DC Characteristics .........................................................................................................................423 Supply Current Characteristics ......................................................................................................427 Analog Comparator (ACMP) Electricals ..
Chapter 1 Device Overview MC9S08DZ128 Series devices are members of the low-cost, high-performance HCS08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available with a variety of modules, memory sizes, memory types, and package types. 1.
Chapter 1 Device Overview t Table 1-1.
Chapter 1 Device Overview Table 1-2 provides the functional version of the on-chip modules. Table 1-2. Module Versions Module 1.
PORT A PTA7/PIA7/ADP7/IRQ PTA6/PIA6/ADP6 PTA5/PIA5/ADP5 PTA4/PIA4/ADP4 PTA3/PIA3/ADP3/ACMP1O PTA2/PIA2/ADP2/ACMP1PTA1/PIA1/ADP1/ACMP1+ PTA0/PIA0/ADP0/MCLK PORT B Chapter 1 Device Overview PTB7/PIB7/ADP15 PTB6/PIB6/ADP14 PTB5/PIB5/ADP13 PTB4/PIB4/ADP12 PTB3/PIB3/ADP11 PTB2/PIB2/ADP10 PTB1/PIB1/ADP9 PTB0/PIB0/ADP8 HCS08 CORE DEBUG MODULE (DBG) CPU BKP ANALOG COMPARATOR (ACMP1) HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT COP LVD INT IRQ VDD VSS REAL-TIME COUNTER
Chapter 1 Device Overview 1.3 System Clock Distribution Figure 1-2 shows a simplified clock connection diagram. Some modules in the MCU have selectable clock inputs as shown. The clock inputs to the modules indicate the clock(s) that are used to drive the module function. The following are the clocks used in this MCU: • BUSCLK — The frequency of the bus is always half of MCGOUT. • LPO — Independent 1-kHz clock that can be selected as the source for the COP and RTC modules.
Chapter 1 Device Overview MC9S08DZ128 Series Data Sheet, Rev.
Chapter 2 Pins and Connections This section describes signals that connect to package pins. It includes pinout diagrams, recommended system connections, and detailed discussions of signals. 2.1 Device Pin Assignment This section shows the pin assignments for MC9S08DZ128 Series MCUs in the available packages. MC9S08DZ128 Series Data Sheet, Rev.
100-Pin LQFP 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PTB1/PIB1/ADP9 PTC2/ADP18 PTA0/PIA0/ADP0/MCLK PTC1/ADP17 PTB0/PIB0/ADP8 PTC0/ADP16 PTH7 PTH6 PTH5 PTH4 BKGD/MS PTD7/PID7/TPM1CH5 PTD6/PID6/TPM1CH4 VDD VSS PTL3 PTF7 PTH3/MISO2 PTH2/MOSI2 PTH1/SPSCK2 PTH0/SS2 PTD5/PID5/TPM1CH3 PTD4/PID4/TPM1CH2 PTD3/PID3/TPM1CH1 PTD2/PID2/TPM1CH0
64-Pin LQFP 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PTB1/PIB1/ADP9 PTC2/ADP18 PTA0/PIA0/ADP0/MCLK PTC1/ADP17 PTB0/PIB0/ADP8 PTC0/ADP16 BKGD/MS PTD7/PID7/TPM1CH5 PTD6/PID6/TPM1CH4 VDD VSS PTF7 PTD5/PID5/TPM1CH3 PTD4/PID4/TPM1CH2 PTD3/PID3/TPM1CH1 PTD2/PID2/TPM1CH0 PTE2/SS1 PTE3/SPSCk1 PTE4/SCL1/MOSI1 PTE5/SDA1/MISO1 PTG2 PTG3 PTF0/TxD2 PTF1/RxD2 PTF2/TPM1CLK/SCL1 PTF3/TPM2CLK/SDA1 PTG4 PTG5 PTE6/TxD2TxCAN PTE7
48-Pin LQFP 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 PTB1/PIB1/ADP9 PTA0/PIA0/ADP0/MCLK PTB0/PIB0/ADP8 BKGD/MS PTD7/PID7/TPM1CH5 PTD6/PID6/TPM1CH4 VDD VSS PTD5/PID5/TPM1CH3 PTD4/PID4/TPM1CH2 PTD3/PID3/TPM1CH1 PTD2/PID2/TPM1CH0 PTE2/SS1 PTE3/SPSCK1 PTE4/SCL1/MOSI1 PTE5/SDA1/MISO1 PTF0/TxD2 PTF1/RxD2 PTF2/TPM1CLK/SCL1 PTF3/TPM2CLK/SDA1 PTE6/TxD2/TXCAN PTE7/RxD2/RXCAN PTD0/PID0/TPM2CH0 PTD1/PID1/TPM2CH1 PTB6/PIB6/ADP14 PTA7/PIA7/ADP7/IRQ PTB7/PIB7
Chapter 2 Pins and Connections 2.2 Recommended System Connections Figure 2-4 shows pin connections that are common to MC9S08DZ128 Series application systems. VDD + 5V MC9S08DZ128 CBY 0.
Chapter 2 Pins and Connections 2.2.1 Power VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides regulated lower-voltage source to the CPU and other internal circuitry of the MCU. Typically, application systems have two separate capacitors across the power pins.
Chapter 2 Pins and Connections Whenever any reset is initiated (whether from an external signal or from an internal system), the RESET pin is driven low for about 34 bus cycles. The reset circuitry decodes the cause of reset and records it by setting a corresponding bit in the system reset status register (SRS). 2.2.4 Background / Mode Select (BKGD/MS) While in reset, the BKGD/MS pin functions as a mode select pin.
Chapter 2 Pins and Connections NOTE To avoid extra current drain from floating input pins, the reset initialization routine in the application program should either enable on-chip pull-up devices or change the direction of unused or non-bonded pins to outputs so they do not float. Table 2-1.
Chapter 2 Pins and Connections Table 2-1.
Chapter 2 Pins and Connections Table 2-1.
Chapter 2 Pins and Connections Table 2-1.
Chapter 2 Pins and Connections MC9S08DZ128 Series Data Sheet, Rev.
Chapter 3 Modes of Operation 3.1 Introduction The operating modes of the MC9S08DZ128 Series are described in this chapter. Entry into each mode, exit from each mode, and functionality while in each of the modes are described. 3.2 • • • 3.
Chapter 3 Modes of Operation Background commands are of two types: • Non-intrusive commands, defined as commands that can be issued while the user program is running. Non-intrusive commands can be issued through the BKGD/MS pin while the MCU is in run mode; non-intrusive commands can also be executed when the MCU is in the active background mode.
Chapter 3 Modes of Operation 3.6 Stop Modes One of two stop modes is entered upon execution of a STOP instruction when the STOPE bit in SOPT1 register is set. In both stop modes, all internal clocks are halted. The MCG module can be configured to leave the reference clocks running. See Chapter 8, “Multi-Purpose Clock Generator (S08MCGV2),” for more information. Table 3-1 shows all of the control bits that affect stop mode selection and the mode selected under various conditions.
Chapter 3 Modes of Operation 3.6.1.2 Active BDM Enabled in Stop3 Mode Entry into the active background mode from run mode is enabled if ENBDM in BDCSCR is set. This register is described in Chapter 17, “Development Support.” If ENBDM is set when the CPU executes a STOP instruction, the system clocks to the background debug logic remain active when the MCU enters stop mode. Because of this, background debug communication remains possible.
Chapter 3 Modes of Operation clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.6.1, “Stop3 Mode” and Section 3.6.1, “Stop3 Mode” for specific information on system behavior in stop modes. Table 3-2.
Chapter 3 Modes of Operation MC9S08DZ128 Series Data Sheet, Rev.
Chapter 4 Memory 4.1 MC9S08DZ128 Series Memory Map On-chip memory in the MC9S08DZ128 Series consists of RAM, EEPROM, and FLASH program memory for nonvolatile data storage, and I/O and control/status registers. The registers are divided into three groups: • Direct-page registers (0x0000 through 0x007F) • High-page registers (0x1800 through 0x18FF) • Nonvolatile registers (0xFFB0 through 0xFFBF) MC9S08DZ128 Series Data Sheet, Rev.
Chapter 4 Memory All 128K bytes of Flash can also be accessed through the linear address pointer.
Chapter 4 Memory 0x0_007F 0x0_0080 DIRECT PAGE REGISTERS 128 BYTES CPU Address 0x0000 0x007F 0x0080 0x1_C000 - 0x1_FFFF 0x1_8000 - 0x1_BFFF All 96K bytes of Flash can also be accessed through the linear address pointer.
Chapter 4 Memory CPU Address 0x0000 0x007F 0x0080 RAM 6016 BYTES 0x17FF 0x1800 0x18FF 0x1900 PPAGE=0 FLASH 9984 BYTES PPAGE=1 FLASH 16384 BYTES 0x0_7FFF 0x0_8000 0x7FFF 0x8000 Paging Window Extended addresses formed with PPAGE and CPU addresses A13:A0 0x0_BFFF 0x0_C000 0x1_4000 - 0x1_7FFF 0x1_0000 - 0x1_3FFF 0x0_C000 - 0x0_FFFF 0x0_8000 - 0x0_BFFF 0x0_4000 - 0x0_7FFF 0x0_0000 - 0x0_3FFF FLASH 16384 BYTES 0xBFFF 0xC000 PPAGE=7 0x3FFF 0x4000 PPAGE=6 0x0_3FFF 0x0_4000 Extended Address 0x1_C000 - 0
Chapter 4 Memory DIRECT PAGE REGISTERS 128 BYTES RAM 4096 BYTES 0x0_007F 0x0_0080 0x0_107F 0x0_1080 CPU Address 0x0000 0x007F 0x0080 0x107F 0x1080 0x1_C000 - 0x1_FFFF 0x1_8000 - 0x1_BFFF All 96K bytes of Flash can also be accessed through the linear address pointer.
Chapter 4 Memory Table 4-1.
Chapter 4 Memory 4.3 Register Addresses and Bit Assignments The registers in the MC9S08DZ128 Series are divided into these groups: • Direct-page registers are located in the first 128 locations in the memory map; these are accessible with efficient direct addressing mode instructions. • High-page registers are used much less often, so they are located above 0x1800 in the memory map. This leaves more room in the direct page for more frequently used registers and RAM.
Chapter 4 Memory Table 4-2.
Chapter 4 Memory Table 4-2.
Chapter 4 Memory Table 4-2.
Chapter 4 Memory Table 4-2.
Chapter 4 Memory Table 4-3.
Chapter 4 Memory Table 4-3.
Chapter 4 Memory Table 4-3.
Chapter 4 Memory Table 4-3.
Chapter 4 Memory Table 4-4.
Chapter 4 Memory debug interface) and verifying that FLASH is blank. To avoid returning to secure mode after the next reset, program the security bits (SEC) to the unsecured state (1:0). 4.4 Memory Management Unit The memory management unit (MMU) allows the program and data space for the HCS08 Family of Microcontrollers to be extended beyond the 64K CPU addressable memory map. The extended memory when used for data can also be accessed linearly using a linear address pointer and data access registers.
Chapter 4 Memory When the MMU detects that the CPU is addressing the Paging Window, the value currently in PPAGE will be used to create an extended address that the MCU’s decode logic will use to select the desired FLASH location. For example, the Flash from location 0x4000-0x7FFF can be accessed directly or using the paging window, PPAGE = 1, address 0x8000-0xBFFF. 4.4.2.
Chapter 4 Memory Accessing either the LBP or LWP registers allows a user program to read successive memory locations without re-writing the linear address pointer. Accessing LBP or LWP does the exact same function. However, because of the address mapping of the registers with LBP following LWP, a user can do word accesses in the extended address space using the LDHX or STHX instructions to access location LWP.
Chapter 4 Memory R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 LA16 W R LA15 LA14 LA13 LA12 LA11 LA10 LA9 LA8 LA7 LA6 LA5 LA4 LA3 LA2 LA1 LA0 0 0 0 0 0 0 0 0 W R W Reset: Figure 4-6. Linear Address Pointer Registers 2:0 (LAP2:LAP0) Table 4-7. Linear Address Pointer Registers 2:0 Field Descriptions Field Description 16:0 LA16:LA0 The values in LAP2:LAP0 are used to create a 17-bit linear address pointer.
Chapter 4 Memory address of the FLASH memory location to be addressed. When accessing data using LBP, the contents of LAP2:LAP0 will increment after the read or write is complete. Accessing LBP does the same thing as accessing LWP. The MMU register ordering of LWP followed by LBP, allow the user to access data by words using the LDHX or STHX instructions with the address of the LWP register. 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 R W Reset: Figure 4-8.
Chapter 4 Memory 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 Reset: Figure 4-10. Linear Address Pointer Add Byte Register (LAPAB) Table 4-11. Linear Address Pointer Add Byte Register Field Descriptions Field 7:0 D7:D0 4.5 Description The 2s complement value written to LAPAB will be added to contents of the linear address pointer register, LAP2:LAP0.
Chapter 4 Memory 4.6 FLASH and EEPROM MC9S08DZ128 Series devices include FLASH and EEPROM memory intended primarily for program and data storage. In-circuit programming allows the operating program and data to be loaded into FLASH and EEPROM, respectively, after final assembly of the application product. It is possible to program the arrays through the single-wire background debug interface.
Chapter 4 Memory Table 4-12 shows program and erase times. The bus clock frequency and FCDIV determine the frequency of FCLK (fFCLK). The time for one cycle of FCLK is tFCLK = 1/fFCLK. The times are shown as a number of cycles of FCLK and as an absolute time for the case where tFCLK = 5 μs. Program and erase times shown include overhead for the command state machine and enabling and disabling of program and erase voltages. Table 4-12. Program and Erase Times 1 4.6.
Chapter 4 Memory A strictly monitored procedure must be obeyed or the command will not be accepted. This minimizes the possibility of any unintended changes to the memory contents. The command complete flag (FCCF) indicates when a command is complete. The command sequence must be completed by clearing FCBEF to launch the command. Figure 4-11 is a flowchart for executing all of the commands except for burst programming and sector erase abort. 4. Wait until the FCCF bit in FSTAT is set.
Chapter 4 Memory a burst program command is issued, the charge pump is enabled and remains enabled after completion of the burst program operation if these two conditions are met: • The next burst program command sequence has begun before the FCCF bit is set. • The next sequential address selects a byte on the same burst block as the current byte being programmed. A burst block in this FLASH memory consists of 32 bytes. A new burst block begins at each 32-byte address boundary.
Chapter 4 Memory (1) Required only once after reset. WRITE TO FCDIV(1) BURST PROGRAM FLOW START 0 FACCERR? 1 CLEAR ERROR FCBEF? 0 1 WRITE TO FLASH TO BUFFER ADDRESS AND DATA WRITE COMMAND TO FCMD WRITE 1 TO FCBEF TO LAUNCH COMMAND AND CLEAR FCBEF (2) FPVIOL OR FACCERR? (2) Wait at least four bus cycles before checking FCBEF or FCCF. YES ERROR EXIT NO YES NEW BURST COMMAND? NO 0 FCCF? 1 DONE Figure 4-12. Burst Program Flowchart MC9S08DZ128 Series Data Sheet, Rev.
Chapter 4 Memory 4.6.5 Sector Erase Abort The sector erase abort operation will terminate the active sector erase operation so that other sectors are available for read and program operations without waiting for the sector erase operation to complete. The sector erase abort command write sequence is as follows: 1. Write to any FLASH or EEPROM address to start the command write sequence for the sector erase abort command. The address and data written are ignored. 2.
Chapter 4 Memory NOTE The FCBEF flag will not set after launching the sector erase abort command. If an attempt is made to start a new command write sequence with a sector erase abort operation active, the FACCERR flag in the FSTAT register will be set. A new command write sequence may be started after clearing the ACCERR flag, if set. NOTE The sector erase abort command should be used sparingly since a sector erase operation that is aborted counts as a complete program/erase cycle. 4.6.
Chapter 4 Memory 4.6.7 Block Protection The block protection feature prevents the protected region of FLASH or EEPROM from program or erase changes. Block protection is controlled through the FLASH and EEPROM protection register (FPROT). The EPS bits determine the protected region of EEPROM and the FPS bits determine the protected region of FLASH. See Section 4.6.11.4, “FLASH and EEPROM Protection Register (FPROT and NVPROT).
Chapter 4 Memory which can be performed at the same time the FLASH memory is programmed. The 1:0 state disengages security; the other three combinations engage security. Notice the erased state (1:1) makes the MCU secure. During development, whenever the FLASH is erased, it is good practice to immediately program the SEC0 bit to 0 in NVOPT so SEC = 1:0. This would allow the MCU to remain unsecured after a subsequent reset. The on-chip debug module cannot be enabled while the MCU is secure.
Chapter 4 Memory 4.6.10 EEPROM Mapping Only half of the EEPROM is in the memory map. The EPGSEL bit in FCNFG register selects which half of the array can be accessed in foreground while the other half can not be accessed in background. There are two mapping mode options that can be selected to configure the 8-byte EEPROM sectors: 4-byte mode and 8-byte mode. Each mode is selected by the EPGMOD bit in the FOPT register.
Chapter 4 Memory Table 4-13. FCDIV Register Field Descriptions Field Description 7 DIVLD Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has been written since reset. Reset clears this bit and the first write to this register causes this bit to become set regardless of the data written. 0 FCDIV has not been written since reset; erase and program operations disabled for FLASH and EEPROM.
Chapter 4 Memory if PRDIV8 = 0 — fFCLK = fBus ÷ (DIV + 1) Eqn. 4-1 if PRDIV8 = 1 — fFCLK = fBus ÷ (8 × (DIV + 1)) Eqn. 4-2 Table 4-14 shows the appropriate values for PRDIV8 and DIV for selected bus frequencies. Table 4-14. FLASH and EEPROM Clock Divider Settings 4.6.11.2 fBus PRDIV8 (Binary) DIV (Decimal) fFCLK Program/Erase Timing Pulse (5 μs Min, 6.7 μs Max) 20 MHz 1 12 192.3 kHz 5.
Chapter 4 Memory Table 4-15. FOPT Register Field Descriptions Field Description 5 EPGMOD EEPROM Sector Mode — When this bit is 0, each sector is split into two pages (4-byte mode). When this bit is 1, each sector is in a single page (8-byte mode). 0 Half of each EEPROM sector is in Page 0 and the other half is in Page 1. 1 Each sector is in a single page. 1:0 SEC Security State Code — This 2-bit field determines the security state of the MCU as shown in Table 4-16.
Chapter 4 Memory 4.6.11.4 FLASH and EEPROM Protection Register (FPROT and NVPROT) The FPROT register defines which FLASH and EEPROM sectors are protected against program and erase operations. During the reset sequence, the FPROT register is loaded from the nonvolatile location NVPROT. To change the protection that will be loaded during the reset sequence, the sector containing NVPROT must be unprotected and erased, then NVPROT can be reprogrammed.
Chapter 4 Memory Table 4-20.
Chapter 4 Memory 4.6.11.5 FLASH and EEPROM Status Register (FSTAT) 7 R 6 5 4 FPVIOL FACCERR 0 0 FCCF FCBEF 3 2 1 0 0 FBLANK 0 0 0 0 0 0 W Reset 1 1 = Unimplemented or Reserved Figure 4-18. FLASH and EEPROM Status Register (FSTAT) Table 4-21. FSTAT Register Field Descriptions Field Description 7 FCBEF Command Buffer Empty Flag — The FCBEF bit is used to launch commands.
Chapter 4 Memory Command Execution,” for a detailed discussion of FLASH and EEPROM programming and erase operations. R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset FCMD 0 0 0 0 Figure 4-19. FLASH and EEPROM Command Register (FCMD) Table 4-22.
Chapter 4 Memory MC9S08DZ128 Series Data Sheet, Rev.
Chapter 5 Resets, Interrupts, and General System Control 5.1 Introduction This section discusses basic reset and interrupt mechanisms and their various sources in the MC9S08DZ128 Series. Some interrupt sources from peripheral modules are discussed in greater detail within other sections of this data sheet. This section gathers basic information about all reset and interrupt sources in one place for easy reference.
Chapter 5 Resets, Interrupts, and General System Control bus cycles. After the 34 cycles are completed, the pin is released and will be pulled up by the internal pull-up resistor, unless it is held low externally. After the pin is released, it is sampled after another 38 cycles to determine whether the reset pin is the cause of the MCU reset. 5.4 Computer Operating Properly (COP) Watchdog The COP watchdog is intended to force a system reset when the application software fails to execute as expected.
Chapter 5 Resets, Interrupts, and General System Control If the 1-kHz clock source is selected, the COP counter is re-initialized to zero upon entry to either background debug mode or stop mode and begins from zero upon exit from background debug mode or stop mode. 5.5 Interrupts Interrupts provide a way to save the current CPU status and registers, execute an interrupt service routine (ISR), and then restore the CPU status so processing resumes where it left off before the interrupt.
Chapter 5 Resets, Interrupts, and General System Control 5.5.1 Interrupt Stack Frame Figure 5-1 shows the contents and organization of a stack frame. Before the interrupt, the stack pointer (SP) points at the next available byte location on the stack. The current values of CPU registers are stored on the stack starting with the low-order byte of the program counter (PCL) and ending with the CCR.
Chapter 5 Resets, Interrupts, and General System Control The IRQ pin, when enabled, defaults to use an internal pull device (IRQPDD = 0), the device is a pull-up or pull-down depending on the polarity chosen. If the user desires to use an external pull-up or pull-down, the IRQPDD can be written to a 1 to turn off the internal device. BIH and BIL instructions may be used to detect the level on the IRQ pin when the pin is configured to act as the IRQ input. 5.5.2.
Chapter 5 Resets, Interrupts, and General System Control Table 5-1.
Chapter 5 Resets, Interrupts, and General System Control Table 5-1.
Chapter 5 Resets, Interrupts, and General System Control 5.6.3 Low-Voltage Warning (LVW) Interrupt Operation The LVD system has a low-voltage warning flag to indicate to the user that the supply voltage is approaching the low-voltage condition. When a low-voltage warning condition is detected and is configured for interrupt operation (LVWIE set to 1), LVWF in SPMSC1 will be set and an LVW interrupt request will occur. 5.7 MCLK Output The PTA0 pin is shared with the MCLK clock output.
Chapter 5 Resets, Interrupts, and General System Control Table 5-2. IRQSC Register Field Descriptions Field Description 6 IRQPDD Interrupt Request (IRQ) Pull Device Disable— This read/write control bit is used to disable the internal pull-up/pull-down device when the IRQ pin is enabled (IRQPE = 1) allowing for an external device to be used. 0 IRQ pull device enabled if IRQPE = 1. 1 IRQ pull device disabled if IRQPE = 1.
Chapter 5 Resets, Interrupts, and General System Control 5.8.2 System Reset Status Register (SRS) This high page register includes read-only status flags to indicate the source of the most recent reset. When a debug host forces reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS will be set. Writing any value to this register address causes a COP reset when the COP is enabled except the values 0x55 and 0xAA.
Chapter 5 Resets, Interrupts, and General System Control Table 5-3. SRS Register Field Descriptions Field Description 2 LOC Loss of Clock — Reset was caused by a loss of external clock. 0 Reset not caused by loss of external clock 1 Reset caused by loss of external clock 1 LVD Low-Voltage Detect — If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset will occur. This bit is also set by POR. 0 Reset not caused by LVD trip or POR. 1 Reset caused by LVD trip or POR. 5.8.
Chapter 5 Resets, Interrupts, and General System Control 5.8.4 System Options Register 1 (SOPT1) This high page register is a write-once register so only the first write after reset is honored. It can be read at any time. Any subsequent attempt to write to SOPT1 (intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings.
Chapter 5 Resets, Interrupts, and General System Control 5.8.5 System Options Register 2 (SOPT2) This high page register contains bits to configure MCU specific features on the MC9S08DZ128 Series devices. R 7 6 5 COPCLKS1 COPW1 0 0 4 3 0 2 1 0 0 ADHTS MCSEL W Reset: 0 0 0 0 0 0 = Unimplemented or Reserved Figure 5-6. System Options Register 2 (SOPT2) 1 This bit can be written only one time after reset. Additional writes are ignored. Table 5-7.
Chapter 5 Resets, Interrupts, and General System Control 5.8.6 System Device Identification Register (SDIDH, SDIDL) These high page read-only registers are included so host development systems can identify the HCS08 derivative and revision number. This allows the development software to recognize where specific memory blocks, registers, and control bits are located in a target MCU.
Chapter 5 Resets, Interrupts, and General System Control 5.8.7 System Power Management Status and Control 1 Register (SPMSC1) This high page register contains status and control bits to support the low-voltage detect function, and to enable the bandage voltage reference for use by the ADC and ACMP modules. This register should be written during the user’s reset initialization program to set the desired controls even if the desired settings are the same as the reset settings.
Chapter 5 Resets, Interrupts, and General System Control 5.8.8 System Power Management Status and Control 2 Register (SPMSC2) This register is used to report the status of the low-voltage warning function, and to configure the stop mode behavior of the MCU. This register should be written during the user’s reset initialization program to set the desired controls even if the desired settings are the same as the reset settings.
Chapter 6 Parallel Input/Output Control This section explains software controls related to parallel input/output (I/O) and pin control. The MC9S08DZ128 Series has up to 11 parallel I/O ports which include a total of up to 87 I/O pins and one input-only pin. See Chapter 2, “Pins and Connections,” for more information about pin assignments and external hardware considerations of these pins.
Chapter 6 Parallel Input/Output Control It is a good programming practice to write to the port data register before changing the direction of a port pin to become an output. This ensures that the pin will not be driven momentarily with an old data value that happened to be in the port data register. PTxDDn D Output Enable Q PTxDn D Output Data Q 1 Port Read Data 0 Input Data Synchronizer BUSCLK Figure 6-1. Parallel I/O Block Diagram 6.
Chapter 6 Parallel Input/Output Control to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load. Because of this, the EMC emissions may be affected by enabling pins as high drive. 6.3 Pin Interrupts Port A, port B, port D, and port J pins can be configured as external interrupt inputs and as an external means of waking the MCU from stop or wait low-power modes. The block diagram for each port interrupt logic is shown Figure 6-2.
Chapter 6 Parallel Input/Output Control PTxSC provided all enabled port inputs are at their deasserted levels. PTxIF will remain set if any enabled port pin is asserted while attempting to clear by writing a 1 to PTxACK. 6.3.3 Pull-up/Pull-down Resistors The port interrupt pins can be configured to use an internal pull-up/pull-down resistor using the associated I/O port pull-up enable register.
Chapter 6 Parallel Input/Output Control Semiconductor-provided equate or header file normally is used to translate these names into the appropriate absolute addresses. 6.5.1 Port A Registers Port A is controlled by the registers listed below. 6.5.1.1 Port A Data Register (PTAD) 7 6 5 4 3 2 1 0 PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-3. Port A Data Register (PTAD) Table 6-1.
Chapter 6 Parallel Input/Output Control 6.5.1.3 Port A Pull Enable Register (PTAPE) 7 6 5 4 3 2 1 0 PTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-5. Internal Pull Enable for Port A Register (PTAPE) Table 6-3. PTAPE Register Field Descriptions Field Description 7:0 Internal Pull Enable for Port A Bits — Each of these control bits determines if the internal pull-up or pull-down PTAPE[7:0] device is enabled for the associated PTA pin.
Chapter 6 Parallel Input/Output Control 6.5.1.5 Port A Drive Strength Selection Register (PTADS) 7 6 5 4 3 2 1 0 PTADS7 PTADS6 PTADS5 PTADS4 PTADS3 PTADS2 PTADS1 PTADS0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-7. Drive Strength Selection for Port A Register (PTADS) Table 6-5.
Chapter 6 Parallel Input/Output Control 6.5.1.7 Port A Interrupt Pin Select Register (PTAPS) 7 6 5 4 3 2 1 0 PTAPS7 PTAPS6 PTAPS5 PTAPS4 PTAPS3 PTAPS2 PTAPS1 PTAPS0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-9. Port A Interrupt Pin Select Register (PTAPS) Table 6-7. PTAPS Register Field Descriptions Field Description 7:0 Port A Interrupt Pin Selects — Each of the PTAPSn bits enable the corresponding port A interrupt pin. PTAPS[7:0] 0 Pin not enabled as interrupt.
Chapter 6 Parallel Input/Output Control 6.5.2 Port B Registers Port B is controlled by the registers listed below. 6.5.2.1 Port B Data Register (PTBD) 7 6 5 4 3 2 1 0 PTBD7 PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-11. Port B Data Register (PTBD) Table 6-9. PTBD Register Field Descriptions Field Description 7:0 PTBD[7:0] Port B Data Register Bits — For port B pins that are inputs, reads return the logic level on the pin.
Chapter 6 Parallel Input/Output Control 6.5.2.3 Port B Pull Enable Register (PTBPE) 7 6 5 4 3 2 1 0 PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-13. Internal Pull Enable for Port B Register (PTBPE) Table 6-11. PTBPE Register Field Descriptions Field Description 7:0 Internal Pull Enable for Port B Bits — Each of these control bits determines if the internal pull-up or pull-down PTBPE[7:0] device is enabled for the associated PTB pin.
Chapter 6 Parallel Input/Output Control 6.5.2.5 Port B Drive Strength Selection Register (PTBDS) 7 6 5 4 3 2 1 0 PTBDS7 PTBDS6 PTBDS5 PTBDS4 PTBDS3 PTBDS2 PTBDS1 PTBDS0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-15. Drive Strength Selection for Port B Register (PTBDS) Table 6-13.
Chapter 6 Parallel Input/Output Control 6.5.2.7 Port B Interrupt Pin Select Register (PTBPS) 7 6 5 4 3 2 1 0 PTBPS7 PTBPS6 PTBPS5 PTBPS4 PTBPS3 PTBPS2 PTBPS1 PTBPS0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-17. Port B Interrupt Pin Select Register (PTBPS) Table 6-15. PTBPS Register Field Descriptions Field Description 7:0 Port B Interrupt Pin Selects — Each of the PTBPSn bits enable the corresponding port B interrupt pin. PTBPS[7:0] 0 Pin not enabled as interrupt.
Chapter 6 Parallel Input/Output Control 6.5.3 Port C Registers Port C is controlled by the registers listed below. 6.5.3.1 Port C Data Register (PTCD) 7 6 5 4 3 2 1 0 PTCD7 PTCD6 PTCD5 PTCD4 PTCD3 PTCD2 PTCD1 PTCD0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-19. Port C Data Register (PTCD) Table 6-17. PTCD Register Field Descriptions Field Description 7:0 PTCD[7:0] Port C Data Register Bits — For port C pins that are inputs, reads return the logic level on the pin.
Chapter 6 Parallel Input/Output Control 6.5.3.3 Port C Pull Enable Register (PTCPE) 7 6 5 4 3 2 1 0 PTCPE7 PTCPE6 PTCPE5 PTCPE4 PTCPE3 PTCPE2 PTCPE1 PTCPE0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-21. Internal Pull Enable for Port C Register (PTCPE) Table 6-19. PTCPE Register Field Descriptions Field Description 7:0 Internal Pull Enable for Port C Bits — Each of these control bits determines if the internal pull-up device is PTCPE[7:0] enabled for the associated PTC pin.
Chapter 6 Parallel Input/Output Control 6.5.3.5 Port C Drive Strength Selection Register (PTCDS) 7 6 5 4 3 2 1 0 PTCDS7 PTCDS6 PTCDS5 PTCDS4 PTCDS3 PTCDS2 PTCDS1 PTCDS0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-23. Drive Strength Selection for Port C Register (PTCDS) Table 6-21.
Chapter 6 Parallel Input/Output Control 6.5.4 Port D Registers Port D is controlled by the registers listed below. 6.5.4.1 Port D Data Register (PTDD) 7 6 5 4 3 2 1 0 PTDD7 PTDD6 PTDD5 PTDD4 PTDD3 PTDD2 PTDD1 PTDD0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-24. Port D Data Register (PTDD) Table 6-22. PTDD Register Field Descriptions Field Description 7:0 PTDD[7:0] Port D Data Register Bits — For port D pins that are inputs, reads return the logic level on the pin.
Chapter 6 Parallel Input/Output Control 6.5.4.3 Port D Pull Enable Register (PTDPE) 7 6 5 4 3 2 1 0 PTDPE7 PTDPE6 PTDPE5 PTDPE4 PTDPE3 PTDPE2 PTDPE1 PTDPE0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-26. Internal Pull Enable for Port D Register (PTDPE) Table 6-24. PTDPE Register Field Descriptions Field Description 7:0 Internal Pull Enable for Port D Bits — Each of these control bits determines if the internal pull-up or pull-down PTDPE[7:0] device is enabled for the associated PTD pin.
Chapter 6 Parallel Input/Output Control 6.5.4.5 Port D Drive Strength Selection Register (PTDDS) 7 6 5 4 3 2 1 0 PTDDS7 PTDDS6 PTDDS5 PTDDS4 PTDDS3 PTDDS2 PTDDS1 PTDDS0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-28. Drive Strength Selection for Port D Register (PTDDS) Table 6-26.
Chapter 6 Parallel Input/Output Control 6.5.4.7 Port D Interrupt Pin Select Register (PTDPS) 7 6 5 4 3 2 1 0 PTDPS7 PTDPS6 PTDPS5 PTDPS4 PTDPS3 PTDPS2 PTDPS1 PTDPS0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-30. Port D Interrupt Pin Select Register (PTDPS) Table 6-28. PTDPS Register Field Descriptions Field Description 7:0 Port D Interrupt Pin Selects — Each of the PTDPSn bits enable the corresponding port D interrupt pin. PTDPS[7:0] 0 Pin not enabled as interrupt.
Chapter 6 Parallel Input/Output Control 6.5.5 Port E Registers Port E is controlled by the registers listed below. 6.5.5.1 Port E Data Register (PTED) 7 6 5 4 3 2 1 0 PTED7 PTED6 PTED5 PTED4 PTED3 PTED2 PTED11 PTED0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-32. Port E Data Register (PTED) 1 Reads of this bit always return the pin value of the associated pin, regardless of the value stored in the port data direction bit. Table 6-30.
Chapter 6 Parallel Input/Output Control 6.5.5.3 Port E Pull Enable Register (PTEPE) 7 6 5 4 3 2 1 0 PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-34. Internal Pull Enable for Port E Register (PTEPE) Table 6-32. PTEPE Register Field Descriptions Field Description 7:0 Internal Pull Enable for Port E Bits — Each of these control bits determines if the internal pull-up device is PTEPE[7:0] enabled for the associated PTE pin.
Chapter 6 Parallel Input/Output Control 6.5.5.5 Port E Drive Strength Selection Register (PTEDS) 7 6 5 4 3 2 1 0 PTEDS7 PTEDS6 PTEDS5 PTEDS4 PTEDS3 PTEDS2 PTEDS11 PTEDS0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-36. Drive Strength Selection for Port E Register (PTEDS) 1 PTEDS1 has no effect on the input-only PTE1 pin. Table 6-34.
Chapter 6 Parallel Input/Output Control 6.5.6 Port F Registers Port F is controlled by the registers listed below. 6.5.6.1 Port F Data Register (PTFD) 7 6 5 4 3 2 1 0 PTFD7 PTFD6 PTFD5 PTFD4 PTFD3 PTFD2 PTFD1 PTFD0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-37. Port F Data Register (PTFD) Table 6-35. PTFD Register Field Descriptions Field Description 7:0 PTFD[7:0] Port F Data Register Bits — For port F pins that are inputs, reads return the logic level on the pin.
Chapter 6 Parallel Input/Output Control 6.5.6.3 Port F Pull Enable Register (PTFPE) 7 6 5 4 3 2 1 0 PTFPE7 PTFPE6 PTFPE5 PTFPE4 PTFPE3 PTFPE2 PTFPE1 PTFPE0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-39. Internal Pull Enable for Port F Register (PTFPE) Table 6-37. PTFPE Register Field Descriptions Field Description 7:0 Internal Pull Enable for Port F Bits — Each of these control bits determines if the internal pull-up device is PTFPE[7:0] enabled for the associated PTF pin.
Chapter 6 Parallel Input/Output Control 6.5.6.5 Port F Drive Strength Selection Register (PTFDS) 7 6 5 4 3 2 1 0 PTFDS7 PTFDS6 PTFDS5 PTFDS4 PTFDS3 PTFDS2 PTFDS1 PTFDS0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-41. Drive Strength Selection for Port F Register (PTFDS) Table 6-39.
Chapter 6 Parallel Input/Output Control 6.5.7 Port G Registers Port G is controlled by the registers listed below. 6.5.7.1 Port G Data Register (PTGD) 7 6 5 4 3 2 1 0 PTGD7 PTGD6 PTGD5 PTGD4 PTGD3 PTGD2 PTGD1 PTGD0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-42. Port G Data Register (PTGD) Table 6-40. PTGD Register Field Descriptions Field Description 7:0 PTGD[7:0] Port G Data Register Bits — For port G pins that are inputs, reads return the logic level on the pin.
Chapter 6 Parallel Input/Output Control 6.5.7.3 Port G Pull Enable Register (PTGPE) 7 6 5 4 3 2 1 0 PTGPE7 PTGPE6 PTGPE5 PTGPE4 PTGPE3 PTGPE2 PTGPE1 PTGPE0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-44. Internal Pull Enable for Port G Register (PTGPE) Table 6-42. PTGPE Register Field Descriptions Field Description 7:0 Internal Pull Enable for Port G Bits — Each of these control bits determines if the internal pull-up device is PTGPE[7:0] enabled for the associated PTG pin.
Chapter 6 Parallel Input/Output Control 6.5.7.5 Port G Drive Strength Selection Register (PTGDS) 7 6 5 4 3 2 1 0 PTGDS7 PTGDS6 PTGDS5 PTGDS4 PTGDS3 PTGDS2 PTGDS1 PTGDS0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-46. Drive Strength Selection for Port G Register (PTGDS) Table 6-44.
Chapter 6 Parallel Input/Output Control 6.5.8 Port H Registers Port H is controlled by the registers listed below. 6.5.8.1 Port H Data Register (PTHD) 7 6 5 4 3 2 1 0 PTHD7 PTHD6 PTHD5 PTHD4 PTHD3 PTHD2 PTHD1 PTHD0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-47. Port H Data Register (PTHD) Table 6-45. PTHD Register Field Descriptions Field Description 7:0 PTHD[7:0] Port H Data Register Bits — For port H pins that are inputs, reads return the logic level on the pin.
Chapter 6 Parallel Input/Output Control 6.5.8.3 Port H Pull Enable Register (PTHPE) 7 6 5 4 3 2 1 0 PTHPE7 PTHPE6 PTHPE5 PTHPE4 PTHPE3 PTHPE2 PTHPE1 PTHPE0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-49. Internal Pull Enable for Port H Register (PTHPE) Table 6-47. PTHPE Register Field Descriptions Field Description 7:0 Internal Pull Enable for Port H Bits — Each of these control bits determines if the internal pull-up device is PTHPE[7:0] enabled for the associated PTH pin.
Chapter 6 Parallel Input/Output Control 6.5.8.5 Port H Drive Strength Selection Register (PTHDS) 7 6 5 4 3 2 1 0 PTHDS7 PTHDS6 PTHDS5 PTHDS4 PTHDS3 PTHDS2 PTHDS1 PTHDS0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-51. Drive Strength Selection for Port H Register (PTHDS) Table 6-49.
Chapter 6 Parallel Input/Output Control 6.5.9 Port J Registers Port J is controlled by the registers listed below. 6.5.9.1 Port J Data Register (PTJD) 7 6 5 4 3 2 1 0 PTJD7 PTJD6 PTJD5 PTJD4 PTJD3 PTJD2 PTJD1 PTJD0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-52. Port J Data Register (PTJD) Table 6-50. PTJD Register Field Descriptions Field Description 7:0 PTJD[7:0] Port J Data Register Bits — For port J pins that are inputs, reads return the logic level on the pin.
Chapter 6 Parallel Input/Output Control 6.5.9.3 Port J Pull Enable Register (PTJPE) 7 6 5 4 3 2 1 0 PTJPE7 PTJPE6 PTJPE5 PTJPE4 PTJPE3 PTJPE2 PTJPE1 PTJPE0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-54. Internal Pull Enable for Port J Register (PTJPE) Table 6-52. PTJPE Register Field Descriptions Field Description 7:0 PTJPE[7:0] Internal Pull Enable for Port J Bits — Each of these control bits determines if the internal pull-up device is enabled for the associated PTJ pin.
Chapter 6 Parallel Input/Output Control 6.5.9.5 Port J Drive Strength Selection Register (PTJDS) 7 6 5 4 3 2 1 0 PTJDS7 PTJDS6 PTJDS5 PTJDS4 PTJDS3 PTJDS2 PTJDS1 PTJDS0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-56. Drive Strength Selection for Port J Register (PTJDS) Table 6-54.
Chapter 6 Parallel Input/Output Control 6.5.9.7 Port J Interrupt Pin Select Register (PTJPS) 7 6 5 4 3 2 1 0 PTJPS7 PTJPS6 PTJPS5 PTJPS4 PTJPS3 PTJPS2 PTJPS1 PTJPS0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-58. Port J Interrupt Pin Select Register (PTJPS) Table 6-56. PTJPS Register Field Descriptions Field Description 7:0 PTJPS[7:0] 6.5.9.8 Port J Interrupt Pin Selects — Each of the PTJPSn bits enable the corresponding port J interrupt pin. 0 Pin not enabled as interrupt.
Chapter 6 Parallel Input/Output Control 6.5.10 Port K Registers Port K is controlled by the registers listed below. 6.5.10.1 Port K Data Register (PTKD) 7 6 5 4 3 2 1 0 PTKD7 PTKD6 PTKD5 PTKD4 PTKD3 PTKD2 PTKD1 PTKD0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-60. Port K Data Register (PTKD) Table 6-58. PTKD Register Field Descriptions Field Description 7:0 PTKD[7:0] Port K Data Register Bits — For port K pins that are inputs, reads return the logic level on the pin.
Chapter 6 Parallel Input/Output Control 6.5.10.3 Port K Pull Enable Register (PTKPE) 7 6 5 4 3 2 1 0 PTKPE7 PTKPE6 PTKPE5 PTKPE4 PTKPE3 PTKPE2 PTKPE1 PTKPE0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-62. Internal Pull Enable for Port K Register (PTKPE) Table 6-60. PTKPE Register Field Descriptions Field Description 7:0 Internal Pull Enable for Port K Bits — Each of these control bits determines if the internal pull-up device is PTKPE[7:0] enabled for the associated PTK pin.
Chapter 6 Parallel Input/Output Control 6.5.10.5 Port K Drive Strength Selection Register (PTKDS) 7 6 5 4 3 2 1 0 PTKDS7 PTKDS6 PTKDS5 PTKDS4 PTKDS3 PTKDS2 PTKDS1 PTKDS0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-64. Drive Strength Selection for Port K Register (PTKDS) Table 6-62.
Chapter 6 Parallel Input/Output Control 6.5.11 Port L Registers Port L is controlled by the registers listed below. 6.5.11.1 Port L Data Register (PTLD) 7 6 5 4 3 2 1 0 PTLD7 PTLD6 PTLD5 PTLD4 PTLD3 PTLD2 PTLD1 PTLD0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-65. Port L Data Register (PTLD) Table 6-63. PTLD Register Field Descriptions Field Description 7:0 PTLD[7:0] Port L Data Register Bits — For port L pins that are inputs, reads return the logic level on the pin.
Chapter 6 Parallel Input/Output Control 6.5.11.3 Port L Pull Enable Register (PTLPE) 7 6 5 4 3 2 1 0 PTLPE7 PTLPE6 PTLPE5 PTLPE4 PTLPE3 PTLPE2 PTLPE1 PTLPE0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-67. Internal Pull Enable for Port L Register (PTLPE) Table 6-65. PTLPE Register Field Descriptions Field Description 7:0 Internal Pull Enable for Port L Bits — Each of these control bits determines if the internal pull-up device is PTLPE[7:0] enabled for the associated PTL pin.
Chapter 6 Parallel Input/Output Control 6.5.11.5 Port L Drive Strength Selection Register (PTLDS) 7 6 5 4 3 2 1 0 PTLDS7 PTLDS6 PTLDS5 PTLDS4 PTLDS3 PTLDS2 PTLDS1 PTLDS0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-69. Drive Strength Selection for Port L Register (PTLDS) Table 6-67.
Chapter 6 Parallel Input/Output Control MC9S08DZ128 Series Data Sheet, Rev.
Chapter 7 Central Processor Unit (S08CPUV5) 7.1 Introduction This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU.
Chapter 7 Central Processor Unit (S08CPUV5) 7.2 Programmer’s Model and CPU Registers Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map. 7 0 ACCUMULATOR A 16-BIT INDEX REGISTER H:X H INDEX REGISTER (HIGH) 8 15 INDEX REGISTER (LOW) 7 X 0 SP STACK POINTER 0 15 PROGRAM COUNTER 7 0 CONDITION CODE REGISTER V 1 1 H I N Z C PC CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-1. CPU Registers 7.2.
Chapter 7 Central Processor Unit (S08CPUV5) 7.2.3 Stack Pointer (SP) This 16-bit address pointer register points at the next available location on the automatic last-in-first-out (LIFO) stack. The stack may be located anywhere in the 64-Kbyte address space that has RAM and can be any size up to the amount of available RAM. The stack is used to automatically save the return address for subroutine calls, the return address and CPU registers during interrupts, and for local variables.
Chapter 7 Central Processor Unit (S08CPUV5) 7 0 CONDITION CODE REGISTER V 1 1 H I N Z C CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-2. Condition Code Register Table 7-1. CCR Register Field Descriptions Field Description 7 V Two’s Complement Overflow Flag — The CPU sets the overflow flag when a two’s complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag.
Chapter 7 Central Processor Unit (S08CPUV5) 7.3 Addressing Modes Addressing modes define the way the CPU accesses operands and data. In the HCS08, memory, status and control registers, and input/output (I/O) ports share a single 64-Kbyte CPU address space. This arrangement means that the same instructions that access variables in RAM can also be used to access I/O and control registers or nonvolatile program space.
Chapter 7 Central Processor Unit (S08CPUV5) the high-order byte is located in the next memory location after the opcode, and the low-order byte is located in the next memory location after that. 7.3.4 Direct Addressing Mode (DIR) In direct addressing mode, the instruction includes the low-order eight bits of an address in the direct page (0x0000–0x00FF).
Chapter 7 Central Processor Unit (S08CPUV5) 7.3.6.5 Indexed, 16-Bit Offset (IX2) This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. 7.3.6.
Chapter 7 Central Processor Unit (S08CPUV5) 3. 4. 5. 6. Fetch the high-order half of the interrupt vector. Fetch the low-order half of the interrupt vector. Delay for one free bus cycle. Fetch three bytes of program information starting at the address indicated by the interrupt vector to fill the instruction queue in preparation for execution of the first instruction in the interrupt service routine.
Chapter 7 Central Processor Unit (S08CPUV5) while the CPU is in stop mode, CPU clocks will resume and the CPU will enter active background mode where other serial background commands can be processed. This ensures that a host development system can still gain access to a target MCU even if it is in stop mode. Recovery from stop mode depends on the particular HCS08 and whether the oscillator was stopped in stop mode. Refer to the Modes of Operation chapter for more details. 7.4.
Chapter 7 Central Processor Unit (S08CPUV5) The RTC instruction is used to terminate subroutines invoked by a CALL instruction. RTC unstacks the PPAGE value and the return address, the queue is refilled, and execution resumes with the next instruction after the corresponding CALL. The actual sequence of operations that occur during execution of RTC is: 1. The return value of the 8-bit PPAGE register is pulled from the stack. 2. The 16-bit return address is pulled from the stack and loaded into the PC. 3.
Chapter 7 Central Processor Unit (S08CPUV5) 7.6 HCS08 Instruction Set Summary Table 7-2 provides a summary of the HCS08 instruction set in all possible addressing modes. The table shows operand construction, execution time in internal bus clock cycles, and cycle-by-cycle details for each addressing mode variation of each instruction.
Chapter 7 Central Processor Unit (S08CPUV5) Operation Object Code Cycles Source Form Address Mode Table 7-2.
Chapter 7 Central Processor Unit (S08CPUV5) Operation Object Code Cycles Source Form Address Mode Table 7-2.
Chapter 7 Central Processor Unit (S08CPUV5) CMP CMP CMP CMP CMP CMP CMP CMP #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP Operation Compare Accumulator with Memory A–M (CCR Updated But Operands Not Changed) Object Code IMM DIR EXT IX2 IX1 IX SP2 SP1 A1 B1 C1 D1 E1 F1 9E D1 9E E1 ii dd hh ll ee ff ff ee ff ff Cycles Source Form Address Mode Table 7-2.
Chapter 7 Central Processor Unit (S08CPUV5) INC opr8a INCA INCX INC oprx8,X INC ,X INC oprx8,SP Operation Increment M ← (M) + $01 A ← (A) + $01 X ← (X) + $01 M ← (M) + $01 M ← (M) + $01 M ← (M) + $01 Object Code Cycles Source Form Address Mode Table 7-2.
Chapter 7 Central Processor Unit (S08CPUV5) Operation Object Code MOV opr8a,opr8a MOV opr8a,X+ MOV #opr8i,opr8a MOV ,X+,opr8a Move (M)destination ← (M)source In IX+/DIR and DIR/IX+ Modes, H:X ← (H:X) + $0001 DIR/DIR DIR/IX+ IMM/DIR IX+/DIR 4E 5E 6E 7E MUL Unsigned multiply X:A ← (X) × (A) INH NEG opr8a NEGA NEGX NEG oprx8,X NEG ,X NEG oprx8,SP Negate M ← – (M) = $00 – (M) (Two’s Complement) A ← – (A) = $00 – (A) X ← – (X) = $00 – (X) M ← – (M) = $00 – (M) M ← – (M) = $00 – (M) M ← – (M) = $00 – (
Chapter 7 Central Processor Unit (S08CPUV5) Operation Object Code Cycles Source Form Address Mode Table 7-2.
Chapter 7 Central Processor Unit (S08CPUV5) SUB SUB SUB SUB SUB SUB SUB SUB #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP Operation Object Code IMM DIR EXT IX2 IX1 IX SP2 SP1 A0 B0 C0 D0 E0 F0 9E D0 9E E0 SWI Software Interrupt PC ← (PC) + $0001 Push (PCL); SP ← (SP) – $0001 Push (PCH); SP ← (SP) – $0001 Push (X); SP ← (SP) – $0001 Push (A); SP ← (SP) – $0001 Push (CCR); SP ← (SP) – $0001 I ← 1; PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte INH TAP Transfer Accumul
Chapter 7 Central Processor Unit (S08CPUV5) Operation Object Code Cycles Source Form Address Mode Table 7-2. Instruction Set Summary (Sheet 9 of 9) Affect on CCR Cyc-by-Cyc Details V11H INZC TXS Transfer Index Reg. to SP SP ← (H:X) – $0001 INH 94 2 fp – 1 1 – – – – – WAIT Enable Interrupts; Wait for Interrupt I bit ← 0; Halt CPU INH 8F 2+ fp...
Chapter 7 Central Processor Unit (S08CPUV5) Table 7-3.
Chapter 7 Central Processor Unit (S08CPUV5) Table 7-3.
Chapter 7 Central Processor Unit (S08CPUV5) MC9S08DZ128 Series Data Sheet, Rev.
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) 8.1 Introduction The multi-purpose clock generator (MCG) module provides several clock source choices for the MCU. The module contains a frequency-locked loop (FLL) and a phase-locked loop (PLL) that are controllable by either an internal or an external reference clock. The module can select either of the FLL or PLL clocks, or either of the internal or external reference clocks as a source for the MCU system clock.
PORT A PTA7/PIA7/ADP7/IRQ PTA6/PIA6/ADP6 PTA5/PIA5/ADP5 PTA4/PIA4/ADP4 PTA3/PIA3/ADP3/ACMP1O PTA2/PIA2/ADP2/ACMP1PTA1/PIA1/ADP1/ACMP1+ PTA0/PIA0/ADP0/MCLK PORT B Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) PTB7/PIB7/ADP15 PTB6/PIB6/ADP14 PTB5/PIB5/ADP13 PTB4/PIB4/ADP12 PTB3/PIB3/ADP11 PTB2/PIB2/ADP10 PTB1/PIB1/ADP9 PTB0/PIB0/ADP8 HCS08 CORE DEBUG MODULE (DBG) CPU BKP ANALOG COMPARATOR (ACMP1) HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT COP LVD INT IRQ VD
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) 8.1.
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) External Reference Clock (XOSC) CME EREFS ERCLKEN MCGERCLK EREFSTEN IRCLKEN MCGIRCLK HGO Clock Monitor CLKS BDIV RANGE / 2n LOC OSCINIT DIV32 MCGOUT n=0-3 DMX32 FLL LP Filter DCOM DCOOUT Lock Detector DCOL RDIV PLLS LOLS LOCK DRS / 2n / 25 MCGFFCLK MCGFFCLKVALID MCGLCLK /2 n=0-7 LP IREFS IREFSTEN Internal Reference Clock TRIM Phase Detector Charge Pump VDIV Internal Filter /(4,8,12,...
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) 8.1.2 Modes of Operation There are several modes of operation for the MCG: • FLL Engaged Internal (FEI) • FLL Engaged External (FEE) • FLL Bypassed Internal (FBI) • FLL Bypassed External (FBE) • PLL Engaged External (PEE) • PLL Bypassed External (PBE) • Bypassed Low Power Internal (BLPI) • Bypassed Low Power External (BLPE) • Stop For details see Section 8.4.1, “Operational Modes. 8.
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) 8.3 Register Definition 8.3.1 MCG Control Register 1 (MCGC1) 7 6 5 4 3 2 1 0 IREFS IRCLKEN IREFSTEN 1 0 0 R CLKS RDIV W Reset: 0 0 0 0 0 Figure 8-3. MCG Control Register 1 (MCGC1) Table 8-1. MCG Control Register 1 Field Descriptions Field Description 7:6 CLKS Clock Source Select — Selects the system clock source. 00 Encoding 0 — Output of FLL or PLL is selected. 01 Encoding 1 — Internal reference clock is selected.
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) Table 8-2. FLL External Reference Divide Factor RDIV 0 1 2 3 4 5 6 7 RANGE:DIV32 0:X 1 2 4 8 16 32 64 128 Divide Factor RANGE:DIV32 1:0 1 2 4 8 16 32 64 128 RANGE:DIV32 1:1 32 64 128 256 512 1024 Reserved Reserved Table 8-3. PLL External Reference Divide Factor RDIV 0 1 2 3 4 5 6 7 Divide Factor 1 2 4 8 16 32 64 128 MC9S08DZ128 Series Data Sheet, Rev.
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) 8.3.2 MCG Control Register 2 (MCGC2) 7 6 5 4 3 2 RANGE HGO LP EREFS 0 0 0 0 1 0 R BDIV ERCLKEN EREFSTEN W Reset: 0 1 0 0 Figure 8-4. MCG Control Register 2 (MCGC2) Table 8-4. MCG Control Register 2 Field Descriptions Field Description 7:6 BDIV Bus Frequency Divider — Selects the amount to divide down the clock source selected by the CLKS bits in the MCGC1 register. This controls the bus frequency.
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) 8.3.3 MCG Trim Register (MCGTRM) 7 R 6 5 4 3 2 1 0 TRIM1 W Figure 8-5. MCG Trim Register (MCGTRM) 1 A value for TRIM is loaded during reset from a factory programmed location when not in any BDM mode. If in a BDM mode, a default value of 0x80 is loaded. Table 8-5.
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) 8.3.4 MCG Status and Control Register (MCGSC) R 7 6 5 4 3 LOLS LOCK PLLST IREFST 0 0 0 1 2 CLKST 1 OSCINIT 0 FTRIM1 W Reset: 0 0 0 Figure 8-6. MCG Status and Control Register (MCGSC) 1 A value for FTRIM is loaded during reset from a factory programmed location when not in any BDM mode. If in a BDM mode, a default value of 0x0 is loaded. Table 8-6.
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) Table 8-6. MCG Status and Control Register Field Descriptions (continued) Field Description 1 OSCINIT OSC Initialization — If the external reference clock is selected by ERCLKEN or by the MCG being in FEE, FBE, PEE, PBE, or BLPE mode, and if EREFS is set, then this bit is set after the initialization cycles of the external oscillator clock have completed.
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) Table 8-7. MCG Control Register 3 Field Descriptions (continued) Field Description 4 DIV32 Divide-by-32 Enable — Controls an additional divide-by-32 factor to the external reference clock for the FLL when RANGE bit is set. When the RANGE bit is 0, this bit has no effect. Writes to this bit are ignored if PLLS bit is set. 0 Divide-by-32 is disabled. 1 Divide-by-32 is enabled when RANGE=1.
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) 8.3.6 MCG Test and Control Register (MCGT) R 7 6 0 0 5 4 3 2 1 0 0 0 0 0 DRST DMX32 W DRS Reset: 0 0 0 0 0 0 0 1 Figure 8-8. MCG Test and Control Register (MCGT) dco_select Table 8-8. MCG Test and Control Register Field Descriptions Field 7:6 5 DMX32 4:1 0 DRST DRS Description Reserved for test, user code should not write 1’s to these bits. DCO Maximum frequency with 32.
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) 8.4 Functional Description 8.4.
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) The nine states of the MCG are shown as a state diagram and are described below. The arrows indicate the allowed movements between the states. 8.4.1.
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) factor, as selected by the DRS and DMX32 bits, times the internal reference frequency. The MCGLCLK is derived from the FLL and the PLL is disabled in a low power state. 8.4.1.4 FLL Bypassed External (FBE) In FLL bypassed external (FBE) mode, the MCGOUT clock is derived from the external reference clock and the FLL is operational but its output clock is not used.
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) 8.4.1.6 PLL Bypassed External (PBE) In PLL bypassed external (PBE) mode, the MCGOUT clock is derived from the external reference clock and the PLL is operational but its output clock is not used. This mode is useful to allow the PLL to acquire its target frequency while the MCGOUT clock is driven from the external reference clock.
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) • BDM mode is not active In bypassed low power external mode, the MCGOUT clock is derived from the external reference clock. The external reference clock which is enabled can be an external crystal/resonator or it can be another external clock source. The PLL and the FLL are disabled at all times in BLPE mode and the MCGLCLK will not be available for BDC communications.
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) 8.4.3 Bus Frequency Divider The BDIV bits can be changed at anytime and the actual switch to the new frequency will occur immediately. 8.4.4 Low Power Bit Usage The low power bit (LP) is provided to allow the FLL or PLL to be disabled and thus conserve power when these systems are not being used. The DRS bit can not be written while LP bit is 1.
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) 8.4.7 Fixed Frequency Clock The MCG presents the divided reference clock as MCGFFCLK for use as an additional clock source. The MCGFFCLK frequency must be no more than 1/4 of the MCGOUT frequency to be valid. When MCGFFCLK is valid then MCGFFCLKVALID is set to 1. When MCGFFCLK is not valid then MCGFFCLKVALID is set to 0. MC9S08DZ128 Series Data Sheet, Rev.
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) 8.5 Initialization / Application Information This section describes how to initialize and configure the MCG module in application. The following sections include examples on how to initialize the MCG and properly switch between the various available modes. 8.5.1 MCG Module Initialization Sequence The MCG comes out of reset configured for FEI mode with the BDIV set for divide-by-2.
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) — If ERCLKEN was set in step 1 or the MCG is in FEE, FBE, PEE, PBE, or BLPE mode, and EREFS was also set in step 1, wait here for the OSCINIT bit to become set indicating that the external clock source has finished its initialization cycles and stabilized. Typical crystal startup times are given in Appendix A, “Electrical Characteristics”. — If in FEE mode, check to make sure the IREFST bit is cleared and the LOCK bit is set before moving on.
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) reference can achieve a high-range maximum DCO output of 39.85 MHz with a multiplier of 1216. When the DRS bit is clear, the 32.768 kHz reference can achieve a mid-range maximum DCO output of 19.92 MHz with a multiplier of 608. In FBI and FEI modes, setting the DMX32 bit is not recommended. If the internal reference is trimmed to a frequency above 32.
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) 1 R is the reference divider selected by the RDIV bits, B is the bus frequency divider selected by the BDIV bits, F is the FLL factor selected by the DRS and DMX32 bits, and M is the multiplier selected by the VDIV bits. This section will include 3 mode switching examples using an 8 MHz external crystal. If using an external clock source less than 1 MHz, the MCG should not be configured for any of the PLL modes (PEE and PBE). 8.5.3.
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) a) BLPE: If a transition through BLPE mode is desired, first set LP (bit 3) in MCGC2 to 1. b) BLPE/PBE: MCGC3 = 0x58 (%01011000) – PLLS (bit 6) set to 1, selects the PLL. At this time, with an RDIV value of %011, the FLL reference divider of 256 is switched to the PLL reference divider of 8 (see Table 8-3), resulting in a reference frequency of 8 MHz/ 8 = 1 MHz.
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) START IN FEI MODE MCGC3 = $58 MCGC2 = $36 IN BLPE MODE ? (LP=1) CHECK NO NO YES OSCINIT = 1 ? MCGC2 = $36 (LP = 0) YES MCGC3 = $11 (DIV32 = 1) MCGC1 = $98 CHECK PLLST = 1? NO YES CHECK NO IREFST = 0? CHECK LOCK = 1? YES CHECK CLKST = %10? NO NO YES MCGC1 = $18 YES ENTER BLPE MODE ? NO CHECK CLKST = %11? YES YES MCGC2 = $3E (LP = 1) NO CONTINUE IN PEE MODE Figure 8-10.
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) 8.5.3.2 Example # 2: Moving from PEE to BLPI Mode: Bus Frequency =16 kHz In this example, the MCG will move through the proper operational modes from PEE mode with an 8MHz crystal configured for an 16 MHz bus frequency (see previous example) to BLPI mode with a 16 kHz bus frequency.First, the code sequence will be described. Then a flowchart will be included which illustrates the sequence. 1.
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) – IREFS (bit 2) set to 1 to select the internal reference clock as the reference clock source – RDIV (bits 5-3) remain unchanged because the reference divider does not affect the internal reference. b) Loop until IREFST (bit 4) in MCGSC is 1, indicating the internal reference clock has been selected as the reference clock source c) Loop until CLKST (bits 3 and 2) in MCGSC are %01, indicating that the internal reference clock is selected to feed MCGOUT 4.
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) START IN PEE MODE MCGC1 = $98 CHECK PLLST = 0? CHECK NO YES CLKST = %10 ? YES ENTER NO OPTIONAL: CHECK LOCK = 1? NO NO BLPE MODE ? YES MCGC1 = $5C YES MCGC2 = $3E (LP = 1) CHECK IREFST = 0? MCGC3 = $18 IN BLPE MODE ? (LP=1) NO YES NO CHECK CLKST = %01? NO YES YES MCGC2 = $36 (LP = 0) MCGC2 = $08 CONTINUE IN BLPI MODE Figure 8-11. Flowchart of PEE to BLPI Mode Transition using an 8 MHz crystal MC9S08DZ128 Series Data Sheet, Rev.
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) 8.5.3.3 Example #3: Moving from BLPI to FEE Mode: External Crystal = 8 MHz, Bus Frequency = 16 MHz In this example, the MCG will move through the proper operational modes from BLPI mode at a 16 kHz bus frequency running off of the internal reference clock (see previous example) to FEE mode using an 8MHz crystal configured for a 16 MHz bus frequency. First, the code sequence will be described.
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) START IN BLPI MODE CHECK NO IREFST = 0? MCGC2 = $00 YES OPTIONAL: CHECK LOCK = 1? NO OPTIONAL: CHECK LOCK = 1? NO YES YES MCGC2 = $36 CHECK CLKST = %00? CHECK NO NO YES OSCINIT = 1 ? CONTINUE YES IN FEE MODE MCGC1 = $18 Figure 8-12. Flowchart of BLPI to FEE Mode Transition using an 8 MHz crystal 8.5.
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) trimming approach to search for the best trim value is recommended. In Example #4: Internal Reference Clock Trim later in this section, this approach will be demonstrated. If a user specified trim value has been found for a device (to replace the factory trim value), this value can be stored in FLASH memory to save the value.
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) Initial conditions: 1) Clock supplied from ATE has 500 μsec duty period 2) MCG configured for internal reference with 8MHz bus START TRIM PROCEDURE TRMVAL = $100 n=1 MEASURE INCOMING CLOCK WIDTH (COUNT = # OF BUS CLOCKS / 8) COUNT < EXPECTED = 500 (RUNNING TOO SLOW) .
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2) MC9S08DZ128 Series Data Sheet, Rev.
Chapter 9 5-V Analog Comparator (S08ACMPV3) 9.1 Introduction The analog comparator module (ACMP) provides a circuit for comparing two analog input voltages or for comparing one analog input voltage to an internal reference voltage. The comparator circuit is designed to operate across the full range of the supply voltage (rail-to-rail operation). All MC9S08DZ128 Series MCUs have two full function ACMPs. MCUs in the 48-pin package have two ACMPs, but the output of ACMP2 is not accessible.
PORT A PTA7/PIA7/ADP7/IRQ PTA6/PIA6/ADP6 PTA5/PIA5/ADP5 PTA4/PIA4/ADP4 PTA3/PIA3/ADP3/ACMP1O PTA2/PIA2/ADP2/ACMP1PTA1/PIA1/ADP1/ACMP1+ PTA0/PIA0/ADP0/MCLK PORT B Chapter 9 5-V Analog Comparator (S08ACMPV3) PTB7/PIB7/ADP15 PTB6/PIB6/ADP14 PTB5/PIB5/ADP13 PTB4/PIB4/ADP12 PTB3/PIB3/ADP11 PTB2/PIB2/ADP10 PTB1/PIB1/ADP9 PTB0/PIB0/ADP8 HCS08 CORE DEBUG MODULE (DBG) CPU BKP ANALOG COMPARATOR (ACMP1) HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT COP LVD INT IRQ VDD VSS
Chapter 9 Analog Comparator (S08ACMPV3) 9.1.2 Features The ACMP has the following features: • Full rail to rail supply operation. • Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator output. • Option to compare to fixed internal bandgap reference voltage. • Option to allow comparator output to be visible on a pin, ACMPxO. • Can operate in stop3 mode 9.1.3 Modes of Operation This section defines the ACMP operation in wait, stop and background debug modes.
Chapter 9 Analog Comparator (S08ACMPV3) Internal Bus Internal Reference ACIE ACBGS ACME ACMPx INTERRUPT REQUEST Status & Control Register ACF ACMPx+ + Interrupt Control - ACMPx- set ACF ACMOD ACOPE Comparator ACMPxO Figure 9-2. Analog Comparator 5V (ACMP5) Block Diagram MC9S08DZ128 Series Data Sheet, Rev.
Chapter 9 Analog Comparator (S08ACMPV3) 9.2 External Signal Description The ACMP has two analog input pins, ACMPx+ and ACMPx- and one digital output pin ACMPxO. Each of these pins can accept an input voltage that varies across the full operating voltage range of the MCU. As shown in Figure 9-2, the ACMPx- pin is connected to the inverting input of the comparator, and the ACMPx+ pin is connected to the comparator non-inverting input if ACBGS is a 0.
Chapter 9 Analog Comparator (S08ACMPV3) 9.3.1.1 ACMPx Status and Control Register (ACMPxSC) ACMPxSC contains the status flag and control bits which are used to enable and configure the ACMP. 7 6 5 4 3 ACME ACBGS ACF ACIE 0 0 0 0 R 2 1 0 ACO ACOPE ACMOD W Reset: 0 0 0 0 = Unimplemented Figure 9-3. ACMPx Status and Control Register Table 9-2.
Chapter 9 Analog Comparator (S08ACMPV3) 9.4 Functional Description The analog comparator can be used to compare two analog input voltages applied to ACMPx+ and ACMPx-; or it can be used to compare an analog input voltage applied to ACMPx- with an internal bandgap reference voltage. ACBGS is used to select between the bandgap reference voltage or the ACMPx+ pin as the input to the non-inverting input of the analog comparator.
Chapter 9 Analog Comparator (S08ACMPV3) MC9S08DZ128 Series Data Sheet, Rev.
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) 10.1 Introduction The 12-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation within an integrated microcontroller system-on-chip. NOTE MC9S08DZ128 Series devices operate at a higher voltage range (2.7 V to 5.5 V) and do not include stop1 mode. Please ignore references to stop1. The ADC channel assignments, alternate clock function, and hardware trigger function are configured as described in Section 10.1.
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) Table 10-1.
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) ADHTS, in the SOPT2 register. The RTC or IRQ can be configured to cause a hardware trigger in run, wait, and stop3 modes. 10.1.
PORT A PTA7/PIA7/ADP7/IRQ PTA6/PIA6/ADP6 PTA5/PIA5/ADP5 PTA4/PIA4/ADP4 PTA3/PIA3/ADP3/ACMP1O PTA2/PIA2/ADP2/ACMP1PTA1/PIA1/ADP1/ACMP1+ PTA0/PIA0/ADP0/MCLK PORT B Chapter 10 Analog-to-Digital Converter (S08ADC12V1) PTB7/PIB7/ADP15 PTB6/PIB6/ADP14 PTB5/PIB5/ADP13 PTB4/PIB4/ADP12 PTB3/PIB3/ADP11 PTB2/PIB2/ADP10 PTB1/PIB1/ADP9 PTB0/PIB0/ADP8 HCS08 CORE DEBUG MODULE (DBG) CPU BKP ANALOG COMPARATOR (ACMP1) HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT COP LVD INT IRQ V
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) 10.1.
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) ADIV ADLPC MODE ADLSMP ADTRG 2 ADCO ADCH 1 ADCCFG complete COCO ADCSC1 ADICLK Compare true AIEN 3 Async Clock Gen ADACK MCU STOP ADCK ÷2 ALTCLK abort transfer sample initialize ••• AD0 convert Control Sequencer ADHWT Bus Clock Clock Divide AIEN 1 Interrupt COCO 2 ADVIN SAR Converter AD27 VREFH Data Registers Sum VREFL Compare true 3 Compare Value Registers ACFGT Value Compare Logic ADCSC2 Figure 10-2.
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) 10.2.1 Analog Power (VDDAD) The ADC analog portion uses VDDAD as its power connection. In some packages, VDDAD is connected internally to VDD. If externally available, connect the VDDAD pin to the same voltage potential as VDD. External filtering may be necessary to ensure clean VDDAD for good results. 10.2.2 Analog Ground (VSSAD) The ADC analog portion uses VSSAD as its ground connection. In some packages, VSSAD is connected internally to VSS.
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) 7 R 6 5 AIEN ADCO 0 0 4 3 2 1 0 1 1 COCO ADCH W Reset: 0 1 1 1 Figure 10-3. Status and Control Register (ADCSC1) Table 10-3. ADCSC1 Field Descriptions Field Description 7 COCO Conversion Complete Flag. The COCO flag is a read-only bit set each time a conversion is completed when the compare function is disabled (ACFE = 0).
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) 10.3.2 Status and Control Register 2 (ADCSC2) The ADCSC2 register controls the compare function, conversion trigger, and conversion active of the ADC module. 7 R 6 5 4 ADTRG ACFE ACFGT 0 0 0 ADACT 3 2 0 0 0 0 1 0 R1 R1 0 0 W Reset: 0 Figure 10-4. Status and Control Register 2 (ADCSC2) 1 Bits 1 and 0 are reserved bits that must always be written to 0. Table 10-5.
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) If the MODE bits are changed, any data in ADCRH becomes invalid. R 7 6 5 4 3 2 1 0 0 0 0 0 ADR11 ADR10 ADR9 ADR8 0 0 0 0 0 0 0 0 W Reset: Figure 10-5. Data Result High Register (ADCRH) 10.3.4 Data Result Low Register (ADCRL) ADCRL contains the lower eight bits of the result of a 12-bit or 10-bit conversion, and all eight bits of an 8-bit conversion.
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) In 10-bit mode, the ADCCVH register holds the upper two bits of the 10-bit compare value (ADCV[9:8]). These bits are compared to the upper two bits of the result following a conversion in 10-bit mode when the compare function is enabled. In 8-bit mode, ADCCVH is not used during compare. 10.3.6 Compare Value Low Register (ADCCVL) This register holds the lower 8 bits of the 12-bit or 10-bit compare value or all 8 bits of the 8-bit compare value.
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) Table 10-6. ADCCFG Register Field Descriptions (continued) Field Description 3:2 MODE Conversion Mode Selection. MODE bits are used to select between 12-, 10-, or 8-bit operation. See Table 10-8. 1:0 ADICLK Input Clock Select. ADICLK bits select the input clock source to generate the internal clock ADCK. See Table 10-9. Table 10-7.
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) used to control the pins associated with channels 0–7 of the ADC module. 7 6 5 4 3 2 1 0 ADPC7 ADPC6 ADPC5 ADPC4 ADPC3 ADPC2 ADPC1 ADPC0 0 0 0 0 0 0 0 0 R W Reset: Figure 10-10. Pin Control 1 Register (APCTL1) Table 10-10. APCTL1 Register Field Descriptions Field Description 7 ADPC7 ADC Pin Control 7. ADPC7 controls the pin associated with channel AD7.
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) Table 10-11. APCTL2 Register Field Descriptions Field Description 7 ADPC15 ADC Pin Control 15. ADPC15 controls the pin associated with channel AD15. 0 AD15 pin I/O control enabled 1 AD15 pin I/O control disabled 6 ADPC14 ADC Pin Control 14. ADPC14 controls the pin associated with channel AD14. 0 AD14 pin I/O control enabled 1 AD14 pin I/O control disabled 5 ADPC13 ADC Pin Control 13. ADPC13 controls the pin associated with channel AD13.
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) Table 10-12. APCTL3 Register Field Descriptions Field Description 7 ADPC23 ADC Pin Control 23. ADPC23 controls the pin associated with channel AD23. 0 AD23 pin I/O control enabled 1 AD23 pin I/O control disabled 6 ADPC22 ADC Pin Control 22. ADPC22 controls the pin associated with channel AD22. 0 AD22 pin I/O control enabled 1 AD22 pin I/O control disabled 5 ADPC21 ADC Pin Control 21. ADPC21 controls the pin associated with channel AD21.
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) 10.4.1 Clock Select and Divide Control One of four clock sources can be selected as the clock source for the ADC module. This clock source is then divided by a configurable value to generate the input clock to the converter (ADCK). The clock is selected from one of the following sources by means of the ADICLK bits. • The bus clock, which is equal to the frequency at which software is executed. This is the default selection following reset.
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) configured for low power operation, long sample time, continuous conversion, and automatic compare of the conversion result to a software determined compare value. 10.4.4.1 Initiating Conversions A conversion is initiated: • Following a write to ADCSC1 (with ADCH bits not all 1s) if software triggered operation is selected. • Following a hardware trigger (ADHWT) event if hardware triggered operation is selected.
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) When a conversion is aborted, the contents of the data registers, ADCRH and ADCRL, are not altered. However, they continue to be the values transferred after the completion of the last successful conversion. If the conversion was aborted by a reset, ADCRH and ADCRL return to their reset states. 10.4.4.4 Power Control The ADC module remains in its idle state until a conversion is initiated.
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) Table 10-13. Total Conversion Time vs. Control Conditions Conversion Type ADICLK ADLSMP Max Total Conversion Time Subsequent continuous 10-bit or 12-bit; fBUS > fADCK/11 xx 1 40 ADCK cycles The maximum total conversion time is determined by the clock source chosen and the divide ratio selected. The clock source is selectable by the ADICLK bits, and the divide ratio is specified by the ADIV bits.
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) ALTCLK for this MCU. Consult the module introduction for information on ALTCLK specific to this MCU. A conversion complete event sets the COCO and generates an ADC interrupt to wake the MCU from wait mode if the ADC interrupt is enabled (AIEN = 1). 10.4.7 MCU Stop3 Mode Operation Stop mode is a low power-consumption standby mode during which most or all clock sources on the MCU are disabled. 10.4.7.
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) 10.5 Initialization Information This section gives an example that provides some basic direction on how to initialize and configure the ADC module. You can configure the module for 8-, 10-, or 12-bit resolution, single or continuous conversion, and a polled or interrupt approach, among many other options. Refer to Table 10-7, Table 10-8, and Table 10-9 for information used in this example.
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) ADCSC1 = 0x41 (%01000001) Bit Bit Bit Bit 7 6 5 4:0 COCO AIEN ADCO ADCH 0 1 0 00001 Read-only flag which is set when a conversion completes Conversion complete interrupt enabled One conversion only (continuous conversions disabled) Input channel 1 selected as ADC input channel ADCRH/L = 0xxx Holds results of conversion. Read high byte (ADCRH) before low byte (ADCRL) so that conversion data cannot be overwritten with data from the next conversion.
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) 10.6 Application Information This section contains information for using the ADC module in applications. The ADC has been designed to be integrated into a microcontroller for use in embedded control applications requiring an A/D converter. 10.6.1 External Pins and Routing The following sections discuss the external pins associated with the ADC module and how they should be used for best results. 10.6.1.
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) 10.6.1.3 Analog Input Pins The external analog inputs are typically shared with digital I/O pins on MCU devices. The pin I/O control is disabled by setting the appropriate control bit in one of the pin control registers. Conversions can be performed on inputs without the associated pin control register bit set. It is recommended that the pin control register bit always be set when using a pin as an analog input.
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) 10.6.2.3 Noise-Induced Errors System noise that occurs during the sample or conversion process can affect the accuracy of the conversion. The ADC accuracy numbers are guaranteed as specified only if the following conditions are met: • There is a 0.1 μF low-ESR capacitor from VREFH to VREFL. • There is a 0.1 μF low-ESR capacitor from VDDAD to VSSAD.
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) For 12-bit conversions the code transitions only after the full code width is present, so the quantization error is −1 lsb to 0 lsb and the code width of each step is 1 lsb. 10.6.2.5 Linearity Errors The ADC may also exhibit non-linearity of several forms. Every effort has been made to reduce these errors but the system should be aware of them because they affect overall accuracy.
Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.1 Introduction The inter-integrated circuit (IIC) provides a method of communication between a number of devices. The interface is designed to operate up to 100 kbps with maximum bus loading and timing. The device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pF.
PORT A PTA7/PIA7/ADP7/IRQ PTA6/PIA6/ADP6 PTA5/PIA5/ADP5 PTA4/PIA4/ADP4 PTA3/PIA3/ADP3/ACMP1O PTA2/PIA2/ADP2/ACMP1PTA1/PIA1/ADP1/ACMP1+ PTA0/PIA0/ADP0/MCLK PORT B Chapter 11 Inter-Integrated Circuit (S08IICV2) PTB7/PIB7/ADP15 PTB6/PIB6/ADP14 PTB5/PIB5/ADP13 PTB4/PIB4/ADP12 PTB3/PIB3/ADP11 PTB2/PIB2/ADP10 PTB1/PIB1/ADP9 PTB0/PIB0/ADP8 HCS08 CORE DEBUG MODULE (DBG) CPU BKP ANALOG COMPARATOR (ACMP1) HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT COP LVD INT IRQ VDD VS
Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.1.
Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.1.4 Block Diagram Figure 11-2 is a block diagram of the IIC. Address Data Bus Interrupt ADDR_DECODE CTRL_REG DATA_MUX FREQ_REG ADDR_REG STATUS_REG DATA_REG Input Sync Start Stop Arbitration Control Clock Control In/Out Data Shift Register Address Compare SCL SDA Figure 11-2. IIC Functional Block Diagram 11.2 External Signal Description This section describes each user-accessible pin signal. 11.2.
Chapter 11 Inter-Integrated Circuit (S08IICV2) Refer to the direct-page register summary in the memory chapter of this document for the absolute address assignments for all IIC registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 11.3.
Chapter 11 Inter-Integrated Circuit (S08IICV2) Table 11-3. IICxF Field Descriptions Field 7–6 MULT 5–0 ICR Description IIC Multiplier Factor. The MULT bits define the multiplier factor, mul. This factor, along with the SCL divider, generates the IIC baud rate. The multiplier factor mul as defined by the MULT bits is provided below. 00 mul = 01 01 mul = 02 10 mul = 04 11 Reserved IIC Clock Rate. The ICR bits are used to prescale the bus clock for bit rate selection.
Chapter 11 Inter-Integrated Circuit (S08IICV2) Table 11-5.
Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.3.3 IIC Control Register (IICxC1) 7 6 5 4 3 IICEN IICIE MST TX TXAK R W Reset 2 1 0 0 0 0 0 0 RSTA 0 0 0 0 0 0 = Unimplemented or Reserved Figure 11-5. IIC Control Register (IICxC1) Table 11-6. IICxC1 Field Descriptions Field Description 7 IICEN IIC Enable. The IICEN bit determines whether the IIC module is enabled. 0 IIC is not enabled 1 IIC is enabled 6 IICIE IIC Interrupt Enable.
Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.3.4 IIC Status Register (IICxS) 7 R 6 TCF 5 4 BUSY IAAS 3 2 0 SRW ARBL 1 0 RXAK IICIF W Reset 1 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 11-6. IIC Status Register (IICxS) Table 11-7. IICxS Field Descriptions Field Description 7 TCF Transfer Complete Flag. This bit is set on the completion of a byte transfer. This bit is only valid during or immediately following a transfer to the IIC module or from the IIC module.
Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.3.5 IIC Data I/O Register (IICxD) 7 6 5 4 3 2 1 0 0 0 0 0 R DATA W Reset 0 0 0 0 Figure 11-7. IIC Data I/O Register (IICxD) Table 11-8. IICxD Field Descriptions Field Description 7–0 DATA Data — In master transmit mode, when data is written to the IICxD, a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data.
Chapter 11 Inter-Integrated Circuit (S08IICV2) Table 11-9. IICxC2 Field Descriptions Field Description 7 GCAEN General Call Address Enable. The GCAEN bit enables or disables general call address. 0 General call address is disabled 1 General call address is enabled 6 ADEXT Address Extension. The ADEXT bit controls the number of bits used for the slave address. 0 7-bit address scheme 1 10-bit address scheme 2–0 AD[10:8] Slave Address.
Chapter 11 Inter-Integrated Circuit (S08IICV2) msb SCL 1 SDA lsb 2 3 4 5 6 7 8 msb 9 AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W Start Signal 1 SDA 3 4 5 6 7 8 Calling Address 3 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D1 D0 1 XX Read/ Ack Write Bit Repeated Start Signal 9 No Ack Bit msb 9 AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W Start Signal 2 Data Byte lsb 2 1 Read/ Ack Write Bit Calling Address msb SCL XXX lsb Stop Signal lsb 2 3 4 5 6 7 8 9 AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.4.1.3 Data Transfer Before successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction specified by the R/W bit sent by the calling master. All transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address information for the slave device Each data byte is 8 bits long.
Chapter 11 Inter-Integrated Circuit (S08IICV2) the transition from master to slave mode does not generate a stop condition. Meanwhile, a status bit is set by hardware to indicate loss of arbitration. 11.4.1.7 Clock Synchronization Because wire-AND logic is performed on the SCL line, a high-to-low transition on the SCL line affects all the devices connected on the bus.
Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.4.2 10-bit Address For 10-bit addressing, 0x11110 is used for the first 5 bits of the first address byte. Various combinations of read/write formats are possible within a transfer that includes 10-bit addressing. 11.4.2.1 Master-Transmitter Addresses a Slave-Receiver The transfer direction is not changed (see Table 11-10).
Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.4.3 General Call Address General calls can be requested in 7-bit address or 10-bit address. If the GCAEN bit is set, the IIC matches the general call address as well as its own slave address. When the IIC responds to a general call, it acts as a slave-receiver and the IAAS bit is set after the address cycle.
Chapter 11 Inter-Integrated Circuit (S08IICV2) Arbitration is lost in the following circumstances: • SDA sampled as a low when the master drives a high during an address or data transmit cycle. • SDA sampled as a low when the master drives a high during the acknowledge bit of a data receive cycle. • A start cycle is attempted when the bus is busy. • A repeated start cycle is requested in slave mode. • A stop condition is detected when the master did not request it.
Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.7 1. 2. 3. 4. 5. 1. 2. 3. 4. 5. 6. 7.
Chapter 11 Inter-Integrated Circuit (S08IICV2) Clear IICIF Master Mode ? Y TX N Y RX Tx/Rx ? Arbitration Lost ? N Last Byte Transmitted ? N Clear ARBL Y RXAK=0 ? Last Byte to Be Read ? N N N Y Y IAAS=1 ? Y IAAS=1 ? Y Address Transfer See Note 1 Y End of Addr Cycle (Master Rx) ? Y Y (Read) 2nd Last Byte to Be Read ? N SRW=1 ? Write Next Byte to IICD Set TXACK =1 Generate Stop Signal (MST = 0) Switch to Rx Mode Generate Stop Signal (MST = 0) Read Data from IICD and Store A
Chapter 11 Inter-Integrated Circuit (S08IICV2) MC9S08DZ128 Series Data Sheet, Rev.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 12.1 Introduction Freescale’s controller area network (MSCAN) is a communication controller implementing the CAN 2.0A/B protocol as defined in the Bosch specification dated September 1991. To fully understand the MSCAN specification, it is recommended that the Bosch specification be read first to gain familiarity with the terms and concepts contained within this document.
PORT A PTA7/PIA7/ADP7/IRQ PTA6/PIA6/ADP6 PTA5/PIA5/ADP5 PTA4/PIA4/ADP4 PTA3/PIA3/ADP3/ACMP1O PTA2/PIA2/ADP2/ACMP1PTA1/PIA1/ADP1/ACMP1+ PTA0/PIA0/ADP0/MCLK PORT B Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) PTB7/PIB7/ADP15 PTB6/PIB6/ADP14 PTB5/PIB5/ADP13 PTB4/PIB4/ADP12 PTB3/PIB3/ADP11 PTB2/PIB2/ADP10 PTB1/PIB1/ADP9 PTB0/PIB0/ADP8 HCS08 CORE DEBUG MODULE (DBG) CPU BKP ANALOG COMPARATOR (ACMP1) HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT COP LVD INT
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 12.1.1 Features The basic features of the MSCAN are as follows: • Implementation of the CAN protocol — Version 2.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 12.1.3 Block Diagram MSCAN Oscillator Clock Bus Clock CANCLK MUX Presc. Tq Clk Receive/ Transmit Engine RXCAN TXCAN Transmit Interrupt Req. Receive Interrupt Req. Message Filtering and Buffering Control and Status Errors Interrupt Req. Wake-Up Interrupt Req. Configuration Registers Wake-Up Low Pass Filter Figure 12-2. MSCAN Block Diagram 12.2 External Signal Description The MSCAN uses two external pins: 12.2.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) CAN node 2 CAN node 1 CAN node n MCU CAN Controller (MSCAN) TXCAN RXCAN Transceiver CAN_H CAN_L CAN Bus Figure 12-3. CAN System 12.3 Register Definition This section describes in detail all the registers and register bits in the MSCAN module. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Table 12-1. CANCTL0 Register Field Descriptions Field Description 7 RXFRM1 Received Frame Flag — This bit is read and clear only. It is set when a receiver has received a valid message correctly, independently of the filter configuration. After it is set, it remains set until cleared by software or reset. Clearing is done by writing a 1. Writing a 0 is ignored. This bit is not valid in loopback mode.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Table 12-1. CANCTL0 Register Field Descriptions (continued) Field Description 1 SLPRQ5 Sleep Mode Request — This bit requests the MSCAN to enter sleep mode, which is an internal power saving mode (see Section 12.5.5.4, “MSCAN Sleep Mode”). The sleep mode request is serviced when the CAN bus is idle, i.e., the module is not receiving a message and all transmit buffers are empty.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 12.3.2 MSCAN Control Register 1 (CANCTL1) The CANCTL1 register provides various control bits and handshake status information of the MSCAN module as described below. 7 6 5 4 3 2 CANE CLKSRC LOOPB LISTEN BORM WUPM 0 0 0 1 0 0 R 1 0 SLPAK INITAK 0 1 W Reset: = Unimplemented Figure 12-5.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Table 12-2. CANCTL1 Register Field Descriptions (continued) Field Description 1 SLPAK Sleep Mode Acknowledge — This flag indicates whether the MSCAN module has entered sleep mode (see Section 12.5.5.4, “MSCAN Sleep Mode”). It is used as a handshake flag for the SLPRQ sleep mode request. Sleep mode is active when SLPRQ = 1 and SLPAK = 1.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Table 12-5. Baud Rate Prescaler 12.3.4 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Prescaler value (P) 0 0 0 0 0 0 1 0 0 0 0 0 1 2 0 0 0 0 1 0 3 0 0 0 0 1 1 4 : : : : : : : 1 1 1 1 1 1 64 MSCAN Bus Timing Register 1 (CANBTR1) The CANBTR1 register configures various CAN bus timing parameters of the MSCAN module.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Table 12-7. Time Segment 2 Values 1 TSEG22 TSEG21 TSEG20 Time Segment 2 0 0 0 1 Tq clock cycle1 0 0 1 2 Tq clock cycles : : : : 1 1 0 7 Tq clock cycles 1 1 1 8 Tq clock cycles This setting is not valid. Please refer to Table 12-35 for valid settings. Table 12-8.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) NOTE The CANRFLG register is held in the reset state1 when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable again as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime when out of initialization mode, except RSTAT[1:0] and TSTAT[1:0] flags which are read-only; write of 1 clears flag; write of 0 is ignored. Table 12-9.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Table 12-9. CANRFLG Register Field Descriptions (continued) Field Description 1 OVRIF Overrun Interrupt Flag — This flag is set when a data overrun condition occurs. If not masked, an error interrupt is pending while this flag is set. 0 No data overrun condition 1 A data overrun detected 0 RXF2 Receive Buffer Full Flag — RXF is set by the MSCAN when a new message is shifted in the receiver FIFO.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Table 12-10. CANRIER Register Field Descriptions Field 7 WUPIE1 6 CSCIE Description Wake-Up Interrupt Enable 0 No interrupt request is generated from this event. 1 A wake-up event causes a Wake-Up interrupt request. CAN Status Change Interrupt Enable 0 No interrupt request is generated from this event. 1 A CAN Status Change event causes an error interrupt request.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) R 7 6 5 4 3 0 0 0 0 0 2 1 0 TXE2 TXE1 TXE0 1 1 1 W Reset: 0 0 0 0 0 = Unimplemented Figure 12-10. MSCAN Transmitter Flag Register (CANTFLG) NOTE The CANTFLG register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0).
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) NOTE The CANTIER register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime when not in initialization mode Table 12-12. CANTIER Register Field Descriptions Field Description 2:0 TXEIE[2:0] 12.3.8 Transmitter Empty Interrupt Enable 0 No interrupt request is generated from this event.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 12.3.9 MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK) The CANTAAK register indicates the successful abort of messages queued for transmission, if requested by the appropriate bits in the CANTARQ register. R 7 6 5 4 3 2 1 0 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0 0 0 0 0 0 0 0 0 W Reset: = Unimplemented Figure 12-13.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) NOTE The CANTBSEL register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK=1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Read: Find the lowest ordered bit set to 1, all other bits will be read as 0 Write: Anytime when not in initialization mode Table 12-15.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1), except bits IDHITx, which are read-only Table 12-16. CANIDAC Register Field Descriptions Field Description 5:4 IDAM[1:0] Identifier Acceptance Mode — The CPU sets these flags to define the identifier acceptance filter organization (see Section 12.5.3, “Identifier Acceptance Filter”). Table 12-17 summarizes the different settings.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 BOHOLD W Reset: 0 0 0 0 0 0 0 0 = Unimplemented Figure 12-16. MSCAN Miscellaneous Register (CANMISC) Read: Anytime Write: Anytime; write of ‘1’ clears flag; write of ‘0’ ignored Table 12-19. CANMISC Register Field Descriptions Field Description 0 BOHOLD Bus-off State Hold Until User Request — If BORM is set in Section 12.3.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 12.3.14 MSCAN Transmit Error Counter (CANTXERR) This register reflects the status of the MSCAN transmit error counter. R 7 6 5 4 3 2 1 0 TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 0 0 0 0 0 0 0 0 W Reset: = Unimplemented Figure 12-18.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Table 12-20. CANIDAR0–CANIDAR3 Register Field Descriptions Field Description 7:0 AC[7:0] Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identifier mask register.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Table 12-22. CANIDMR0–CANIDMR3 Register Field Descriptions Field Description 7:0 AM[7:0] Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier acceptance register must be the same as its identifier bit before a match is detected. The message is accepted if all such bits match.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Table 12-24.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Register Name IDR0 IDR1 R W R W R IDR2 W IDR3 W R R DSR0 W R DSR1 W R DSR2 W DSR3 W R R DSR4 W R DSR5 W DSR6 W R R DSR7 W Bit 7 6 5 4 3 2 1 Bit0 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ID18 SRR(1) IDE(1) ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR2 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 D
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Section 12.3.10, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). For receive buffers, only when RXF flag is set (see Section 12.3.4.1, “MSCAN Receiver Flag Register (CANRFLG)”). Write: For transmit buffers, anytime when TXEx flag is set (see Section 12.3.6, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 12.3.10, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”).
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Table 12-25. IDR0 Register Field Descriptions — Extended Field Description 7:0 ID[28:21] Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 7 6 5 4 3 2 1 0 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR x x x x x x x x R W Reset: Figure 12-28. Identifier Register 3 (IDR3) — Extended Identifier Mapping Table 12-28. IDR3 Register Field Descriptions — Extended Field Description 7:1 ID[6:0] Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Table 12-30. IDR1 Register Field Descriptions Field Description 7:5 ID[2:0] Standard Format Identifier — The identifiers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. See also ID bits in Table 12-29.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 7 6 5 4 3 2 1 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 x x x x x x x x R W Reset: Figure 12-33. Data Segment Registers (DSR0–DSR7) — Extended Identifier Mapping Table 12-31. DSR0–DSR7 Register Field Descriptions Field Description 7:0 DB[7:0] Data bits 7:0 12.4.4 Data Length Register (DLR) This register keeps the data length field of the CAN frame.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Table 12-33. Data Length Codes Data Length Code 12.4.5 DLC3 DLC2 DLC1 DLC0 Data Byte Count 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 Transmit Buffer Priority Register (TBPR) This register defines the local priority of the associated message transmit buffer.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Section 12.3.1, “MSCAN Control Register 0 (CANCTL0)”). In case of a transmission, the CPU can only read the time stamp after the respective transmit buffer has been flagged empty. The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The CPU can only read the time stamp registers.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 12.5.2 Message Storage CAN Receive / Transmit Engine CPU12 Memory Mapped I/O Rx0 RXF CPU bus RxFG RxBG MSCAN Rx1 Rx2 Rx3 Rx4 Receiver TxBG Tx0 MSCAN TxFG Tx1 Transmitter TxBG Tx2 TXE0 PRIO TXE1 CPU bus PRIO TXE2 PRIO Figure 12-38. User Model for Message Buffer Organization MSCAN facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 12.5.2.1 Message Transmit Background Modern application layer software is built upon two fundamental assumptions: • Any CAN node is able to send out a stream of scheduled messages without releasing the CAN bus between the two messages. Such nodes arbitrate for the CAN bus immediately after sending the previous message and only release the CAN bus in case of lost arbitration.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) The MSCAN then schedules the message for transmission and signals the successful transmission of the buffer by setting the associated TXE flag. A transmit interrupt (see Section 12.5.7.2, “Transmit Interrupt”) is generated1 when TXEx is set and can be used to drive the application software to re-load the buffer.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) field of the CAN frame, is received into the next available RxBG. If the MSCAN receives an invalid message in its RxBG (wrong identifier, transmission errors, etc.) the actual contents of the buffer will be over-written by the next message. The buffer will then not be shifted into the FIFO.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) • • • Four identifier acceptance filters, each to be applied to — a) the 14 most significant bits of the extended identifier plus the SRR and IDE bits of CAN 2.0B messages or — b) the 11 bits of the standard identifier, the RTR and IDE bits of CAN 2.0A/B messages. Figure 12-40 shows how the first 32-bit filter bank (CANIDAR0–CANIDA3, CANIDMR0–3CANIDMR) produces filter 0 and 1 hits.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) CAN 2.0B Extended Identifier ID28 IDR0 ID21 ID20 IDR1 CAN 2.0A/B Standard Identifier ID10 IDR0 ID3 ID2 IDR1 AM7 CANIDMR0 AM0 AM7 CANIDMR1 AM0 AC7 CANIDAR0 AC0 AC7 CANIDAR1 AC0 ID15 IDE ID14 IDR2 ID7 ID6 IDR3 RTR ID10 IDR2 ID3 ID10 IDR3 ID3 ID Accepted (Filter 0 Hit) AM7 CANIDMR2 AM0 AM7 CANIDMR3 AM0 AC7 CANIDAR2 AC0 AC7 CANIDAR3 AC0 ID Accepted (Filter 1 Hit) Figure 12-40.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) CAN 2.0B Extended Identifier ID28 IDR0 ID21 ID20 IDR1 CAN 2.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) bit position in the filter register. Finally, registers CANIDAR0/1/2/3 determine the value of those bits determined by CANIDMR0/1/2/3. For instance in the case of the filter value of: 0001x1001x0 The CANIDMR0/1/2/3 register would be configured as: 00001000010 and so all message identifier bits except bit 1 and bit 6 would be compared against the CANIDAR0/1/2/3 registers.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 12.5.3.2 Protocol Violation Protection The MSCAN protects the user from accidentally violating the CAN protocol through programming errors. The protection logic implements the following features: • The receive and transmit error counters cannot be written or otherwise manipulated. • All registers which control the configuration of the MSCAN cannot be modified while the MSCAN is on-line. The MSCAN has to be in Initialization Mode.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) If the bus clock is generated from a PLL, it is recommended to select the oscillator clock rather than the bus clock due to jitter considerations, especially at the faster CAN bus rates. PLL lock may also be too wide to ensure adequate clock tolerance. For microcontrollers without a clock and reset generator (CRG), CANCLK is driven from the crystal oscillator (oscillator clock).
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Table 12-34. Time Segment Syntax Syntax Description System expects transitions to occur on the CAN bus during this period. SYNC_SEG Transmit Point A node in transmit mode transfers a new value to the CAN bus at this point. Sample Point A node in receive mode samples the CAN bus at this point. If the three samples per bit option is selected, then this point marks the position of the third sample.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 12.5.4.3 Emulation Modes In all emulation modes, the MSCAN module behaves just like normal system operation modes as described within this specification. 12.5.4.4 Listen-Only Mode In an optional CAN bus monitoring mode (listen-only), the CAN node is able to receive valid data frames and valid remote frames, but it sends only “recessive” bits on the CAN bus. In addition, it cannot start a transmision.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Table 12-36. CPU vs.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 12.5.5.4 MSCAN Sleep Mode The CPU can request the MSCAN to enter this low power mode by asserting the SLPRQ bit in the CANCTL0 register.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) If the WUPE bit in CANCLT0 is not asserted, the MSCAN will mask any activity it detects on CAN. The RXCAN pin is therefore held internally in a recessive state. This locks the MSCAN in sleep mode (Figure 12-45). WUPE must be set before entering sleep mode to take effect. MC9S08DZ128 Series Data Sheet, Rev.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) The MSCAN is able to leave sleep mode (wake up) only when: • CAN bus activity occurs and WUPE = 1 or • the CPU clears the SLPRQ bit NOTE The CPU cannot clear the SLPRQ bit before sleep mode (SLPRQ = 1 and SLPAK = 1) is active. After wake-up, the MSCAN waits for 11 consecutive recessive bits to synchronize to the CAN bus. As a consequence, if the MSCAN is woken-up by a CAN frame, this frame is not received.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 12.5.5.5 MSCAN Initialization Mode In initialization mode, any on-going transmission or reception is immediately aborted and synchronization to the CAN bus is lost, potentially causing CAN protocol violations. To protect the CAN bus system from fatal consequences of violations, the MSCAN immediately drives the TXCAN pin into a recessive state.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 12.5.5.6 MSCAN Power Down Mode The MSCAN is in power down mode (Table 12-36) when • CPU is in stop mode or • CPU is in wait mode and the CSWAI bit is set When entering the power down mode, the MSCAN immediately stops all ongoing transmissions and receptions, potentially causing CAN protocol violations.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 12.5.7.1 Description of Interrupt Operation The MSCAN supports four interrupt vectors (see Table 12-37), any of which can be individually masked (for details see sections from Section 12.3.5, “MSCAN Receiver Interrupt Enable Register (CANRIER),” to Section 12.3.7, “MSCAN Transmitter Interrupt Enable Register (CANTIER)”). NOTE The dedicated interrupt vector addresses are defined in the Resets and Interrupts chapter. Table 12-37.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Section 12.3.4.1, “MSCAN Receiver Flag Register (CANRFLG)” and Section 12.3.5, “MSCAN Receiver Interrupt Enable Register (CANRIER)”). 12.5.7.6 Interrupt Acknowledge Interrupts are directly associated with one or more status flags in either the Section 12.3.4.1, “MSCAN Receiver Flag Register (CANRFLG)” or the Section 12.3.6, “MSCAN Transmitter Flag Register (CANTFLG).” Interrupts are pending as long as one of the corresponding flags is set.
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 12.6.2 Bus-Off Recovery The bus-off recovery is user configurable. The bus-off state can either be exited automatically or on user request. For reasons of backwards compatibility, the MSCAN defaults to automatic recovery after reset. In this case, the MSCAN will become error active again after counting 128 occurrences of 11 consecutive recessive bits on the CAN bus (See the Bosch CAN specification for details).
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) MC9S08DZ128 Series Data Sheet, Rev.
Chapter 13 Serial Peripheral Interface (S08SPIV3) 13.1 Introduction The serial peripheral interface (SPI) module provides for full-duplex, synchronous, serial communication between the MCU and peripheral devices. These peripheral devices can include other microcontrollers, analog-to-digital converters, shift registers, sensors, memories, etc. The SPI runs at a baud rate up to the bus clock divided by two in master mode and up to the bus clock divided by four in slave mode.
PORT A PTA7/PIA7/ADP7/IRQ PTA6/PIA6/ADP6 PTA5/PIA5/ADP5 PTA4/PIA4/ADP4 PTA3/PIA3/ADP3/ACMP1O PTA2/PIA2/ADP2/ACMP1PTA1/PIA1/ADP1/ACMP1+ PTA0/PIA0/ADP0/MCLK PORT B Chapter 13 Serial Peripheral Interface (S08SPIV3) PTB7/PIB7/ADP15 PTB6/PIB6/ADP14 PTB5/PIB5/ADP13 PTB4/PIB4/ADP12 PTB3/PIB3/ADP11 PTB2/PIB2/ADP10 PTB1/PIB1/ADP9 PTB0/PIB0/ADP8 HCS08 CORE DEBUG MODULE (DBG) CPU BKP ANALOG COMPARATOR (ACMP1) HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT COP LVD INT IRQ VDD
Chapter 13 Serial Peripheral Interface (S08SPIV3) 13.1.1 Features Features of the SPI module include: • Master or slave mode operation • Full-duplex or single-wire bidirectional option • Programmable transmit bit rate • Double-buffered transmit and receive • Serial clock phase and polarity options • Slave select output • Selectable MSB-first or LSB-first shifting 13.1.
Chapter 13 Serial Peripheral Interface (S08SPIV3) The most common uses of the SPI system include connecting simple shift registers for adding input or output ports or connecting small peripheral devices such as serial A/D or D/A converters. Although Figure 13-2 shows a system where data is exchanged between two MCUs, many practical systems involve simpler connections where data is unidirectionally transferred from the master MCU to a slave or from a slave to the master MCU. 13.1.2.
Chapter 13 Serial Peripheral Interface (S08SPIV3) PIN CONTROL M SPE MOSI (MOMI) S Tx BUFFER (WRITE SPIxD) ENABLE SPI SYSTEM M SHIFT OUT SPI SHIFT REGISTER SHIFT IN MISO (SISO) S SPC0 Rx BUFFER (READ SPIxD) BIDIROE SHIFT DIRECTION LSBFE SHIFT CLOCK Rx BUFFER FULL Tx BUFFER EMPTY MASTER CLOCK BUS RATE CLOCK SPIBR CLOCK GENERATOR MSTR CLOCK LOGIC SLAVE CLOCK MASTER/SLAVE M SPSCK S MASTER/ SLAVE MODE SELECT MODFEN SSOE MODE FAULT DETECTION SS SPRF SPTEF SPTIE MODF SPIE SPI INTERRUPT
Chapter 13 Serial Peripheral Interface (S08SPIV3) BUS CLOCK PRESCALER CLOCK RATE DIVIDER DIVIDE BY 1, 2, 3, 4, 5, 6, 7, or 8 DIVIDE BY 2, 4, 8, 16, 32, 64, 128, or 256 SPPR2:SPPR1:SPPR0 SPR2:SPR1:SPR0 MASTER SPI BIT RATE Figure 13-4. SPI Baud Rate Generation 13.2 External Signal Description The SPI optionally shares four port pins. The function of these pins depends on the settings of SPI control bits.
Chapter 13 Serial Peripheral Interface (S08SPIV3) 13.3 Modes of Operation 13.3.1 SPI in Stop Modes The SPI is disabled in all stop modes, regardless of the settings before executing the STOP instruction. During either stop1 or stop2 mode, the SPI module will be fully powered down. Upon wake-up from stop1 or stop2 mode, the SPI module will be in the reset state. During stop3 mode, clocks to the SPI module are halted. No registers are affected.
Chapter 13 Serial Peripheral Interface (S08SPIV3) Table 13-1. SPIxC1 Field Descriptions (continued) Field Description 4 MSTR Master/Slave Mode Select 0 SPI module configured as a slave SPI device 1 SPI module configured as a master SPI device 3 CPOL Clock Polarity — This bit effectively places an inverter in series with the clock signal from a master SPI or to a slave SPI device. Refer to Section 13.5.1, “SPI Clock Formats” for more details.
Chapter 13 Serial Peripheral Interface (S08SPIV3) Table 13-3. SPIxC2 Register Field Descriptions Field Description 4 MODFEN Master Mode-Fault Function Enable — When the SPI is configured for slave mode, this bit has no meaning or effect. (The SS pin is the slave select input.) In master mode, this bit determines how the SS pin is used (refer to Table 13-2 for more details).
Chapter 13 Serial Peripheral Interface (S08SPIV3) Table 13-5. SPI Baud Rate Prescaler Divisor SPPR2:SPPR1:SPPR0 Prescaler Divisor 0:0:0 1 0:0:1 2 0:1:0 3 0:1:1 4 1:0:0 5 1:0:1 6 1:1:0 7 1:1:1 8 Table 13-6. SPI Baud Rate Divisor 13.4.4 SPR2:SPR1:SPR0 Rate Divisor 0:0:0 2 0:0:1 4 0:1:0 8 0:1:1 16 1:0:0 32 1:0:1 64 1:1:0 128 1:1:1 256 SPI Status Register (SPIxS) This register has three read-only status bits. Bits 6, 3, 2, 1, and 0 are not implemented and always read 0.
Chapter 13 Serial Peripheral Interface (S08SPIV3) Table 13-7. SPIxS Register Field Descriptions Field Description 7 SPRF SPI Read Buffer Full Flag — SPRF is set at the completion of an SPI transfer to indicate that received data may be read from the SPI data register (SPIxD). SPRF is cleared by reading SPRF while it is set, then reading the SPI data register.
Chapter 13 Serial Peripheral Interface (S08SPIV3) 13.5 Functional Description An SPI transfer is initiated by checking for the SPI transmit buffer empty flag (SPTEF = 1) and then writing a byte of data to the SPI data register (SPIxD) in the master SPI device.
Chapter 13 Serial Peripheral Interface (S08SPIV3) pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1). The master SS output goes to active low one-half SPSCK cycle before the start of the transfer and goes back high at the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a slave. BIT TIME # (REFERENCE) 1 2 ...
Chapter 13 Serial Peripheral Interface (S08SPIV3) in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave.
Chapter 13 Serial Peripheral Interface (S08SPIV3) 13.5.2 SPI Interrupts There are three flag bits, two interrupt mask bits, and one interrupt vector associated with the SPI system. The SPI interrupt enable mask (SPIE) enables interrupts from the SPI receiver full flag (SPRF) and mode fault flag (MODF). The SPI transmit interrupt enable mask (SPTIE) enables interrupts from the SPI transmit buffer empty flag (SPTEF).
Chapter 13 Serial Peripheral Interface (S08SPIV3) MC9S08DZ128 Series Data Sheet, Rev.
Chapter 14 Serial Communications Interface (S08SCIV4) 14.1 Introduction All MCUs in the MC9S08DZ128 Series include SCI1 and SCI2. NOTE MC9S08DZ128 Series devices operate at a higher voltage range (2.7 V to 5.5 V) and do not include stop1 mode. Please ignore references to stop1. 14.1.1 SCI2 Configuration Information The SCI2 module pins, TxD2 and RxD2 can be repositioned under software control using SCI2PS in SOPT1 as shown in Table 14-1.
PORT A PTA7/PIA7/ADP7/IRQ PTA6/PIA6/ADP6 PTA5/PIA5/ADP5 PTA4/PIA4/ADP4 PTA3/PIA3/ADP3/ACMP1O PTA2/PIA2/ADP2/ACMP1PTA1/PIA1/ADP1/ACMP1+ PTA0/PIA0/ADP0/MCLK PORT B Chapter 14 Serial Communications Interface (S08SCIV4) PTB7/PIB7/ADP15 PTB6/PIB6/ADP14 PTB5/PIB5/ADP13 PTB4/PIB4/ADP12 PTB3/PIB3/ADP11 PTB2/PIB2/ADP10 PTB1/PIB1/ADP9 PTB0/PIB0/ADP8 HCS08 CORE DEBUG MODULE (DBG) CPU BKP ANALOG COMPARATOR (ACMP1) HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT COP LVD INT IRQ
Chapter 14 Serial Communications Interface (S08SCIV4) 14.1.
Chapter 14 Serial Communications Interface (S08SCIV4) 14.1.4 Block Diagram Figure 14-2 shows the transmitter portion of the SCI.
Chapter 14 Serial Communications Interface (S08SCIV4) Figure 14-3 shows the receiver portion of the SCI.
Chapter 14 Serial Communications Interface (S08SCIV4) 14.2 Register Definition The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for transmit/receive data. Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all SCI registers. This section refers to registers and control bits only by their names.
Chapter 14 Serial Communications Interface (S08SCIV4) 7 6 5 4 3 2 1 0 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 0 0 0 0 0 1 0 0 R W Reset Figure 14-5. SCI Baud Rate Register (SCIxBDL) Table 14-3. SCIxBDL Field Descriptions Field 7:0 SBR[7:0] 14.2.2 Description Baud Rate Modulo Divisor — These 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo divide rate for the SCI baud rate generator.
Chapter 14 Serial Communications Interface (S08SCIV4) Table 14-4. SCIxC1 Field Descriptions (continued) Field 3 WAKE Description Receiver Wakeup Method Select — Refer to Section 14.3.3.2, “Receiver Wakeup Operation” for more information. 0 Idle-line wakeup. 1 Address-mark wakeup. 2 ILT Idle Line Type Select — Setting this bit to 1 ensures that the stop bit and logic 1 bits at the end of a character do not count toward the 10 or 11 bit times of logic high level needed by the idle line detection logic.
Chapter 14 Serial Communications Interface (S08SCIV4) Table 14-5. SCIxC2 Field Descriptions (continued) Field Description 3 TE Transmitter Enable 0 Transmitter off. 1 Transmitter on. TE must be 1 in order to use the SCI transmitter. When TE = 1, the SCI forces the TxD pin to act as an output for the SCI system. When the SCI is configured for single-wire operation (LOOPS = RSRC = 1), TXDIR controls the direction of traffic on the single SCI communication line (TxD pin).
Chapter 14 Serial Communications Interface (S08SCIV4) Table 14-6. SCIxS1 Field Descriptions Field Description 7 TDRE Transmit Data Register Empty Flag — TDRE is set out of reset and when a transmit data value transfers from the transmit data buffer to the transmit shifter, leaving room for a new character in the buffer. To clear TDRE, read SCIxS1 with TDRE = 1 and then write to the SCI data register (SCIxD). 0 Transmit data register (buffer) full. 1 Transmit data register (buffer) empty.
Chapter 14 Serial Communications Interface (S08SCIV4) Table 14-6. SCIxS1 Field Descriptions (continued) Field Description 1 FE Framing Error Flag — FE is set at the same time as RDRF when the receiver detects a logic 0 where the stop bit was expected. This suggests the receiver was not properly aligned to a character frame. To clear FE, read SCIxS1 with FE = 1 and then read the SCI data register (SCIxD). 0 No framing error detected. This does not guarantee the framing is correct. 1 Framing error.
Chapter 14 Serial Communications Interface (S08SCIV4) Table 14-7. SCIxS2 Field Descriptions (continued) Field 1 LBKDE 0 RAF 1 Description LIN Break Detection Enable— LBKDE is used to select a longer break character detection length. While LBKDE is set, framing error (FE) and receive data register full (RDRF) flags are prevented from setting. 0 Break character is detected at length of 10 bit times (11 if M = 1). 1 Break character is detected at length of 11 bit times (12 if M = 1).
Chapter 14 Serial Communications Interface (S08SCIV4) Table 14-8. SCIxC3 Field Descriptions (continued) Field 4 TXINV1 1 Description Transmit Data Inversion — Setting this bit reverses the polarity of the transmitted data output. 0 Transmit data not inverted 1 Transmit data inverted 3 ORIE Overrun Interrupt Enable — This bit enables the overrun flag (OR) to generate hardware interrupt requests. 0 OR interrupts disabled (use polling). 1 Hardware interrupt requested when OR = 1.
Chapter 14 Serial Communications Interface (S08SCIV4) MODULO DIVIDE BY (1 THROUGH 8191) BUSCLK SBR12:SBR0 BAUD RATE GENERATOR OFF IF [SBR12:SBR0] = 0 DIVIDE BY 16 Tx BAUD RATE Rx SAMPLING CLOCK (16 × BAUD RATE) BAUD RATE = BUSCLK [SBR12:SBR0] × 16 Figure 14-12. SCI Baud Rate Generation SCI communications require the transmitter and receiver (which typically derive baud rates from independent clock sources) to use the same baud rate.
Chapter 14 Serial Communications Interface (S08SCIV4) Writing 0 to TE does not immediately release the pin to be a general-purpose I/O pin. Any transmit activity that is in progress must first be completed. This includes data characters in progress, queued idle characters, and queued break characters. 14.3.2.1 Send Break and Queued Idle The SBK control bit in SCIxC2 is used to send break characters which were originally used to gain the attention of old teletype receivers.
Chapter 14 Serial Communications Interface (S08SCIV4) flag is set. If RDRF was already set indicating the receive data register (buffer) was already full, the overrun (OR) status flag is set and the new data is lost. Because the SCI receiver is double-buffered, the program has one full character time after RDRF is set before the data in the receive data buffer must be read to avoid a receiver overrun.
Chapter 14 Serial Communications Interface (S08SCIV4) message characters. At the end of a message, or at the beginning of the next message, all receivers automatically force RWU to 0 so all receivers wake up in time to look at the first character(s) of the next message. 14.3.3.2.1 Idle-Line Wakeup When WAKE = 0, the receiver is configured for idle-line wakeup. In this mode, RWU is cleared automatically when the receiver detects a full character time of the idle-line level.
Chapter 14 Serial Communications Interface (S08SCIV4) Instead of hardware interrupts, software polling may be used to monitor the TDRE and TC status flags if the corresponding TIE or TCIE local interrupt masks are 0s. When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive data register by reading SCIxD. The RDRF flag is cleared by reading SCIxS1 while RDRF = 1 and then reading SCIxD.
Chapter 14 Serial Communications Interface (S08SCIV4) 14.3.5.2 Stop Mode Operation During all stop modes, clocks to the SCI module are halted. In stop1 and stop2 modes, all SCI register data is lost and must be re-initialized upon recovery from these two stop modes. No SCI module registers are affected in stop3 mode. The receive input active edge detect circuit is still active in stop3 mode, but not in stop2. .
Chapter 14 Serial Communications Interface (S08SCIV4) MC9S08DZ128 Series Data Sheet, Rev.
Chapter 15 Real-Time Counter (S08RTCV1) 15.1 Introduction The RTC module consists of one 8-bit counter, one 8-bit comparator, several binary-based and decimal-based prescaler dividers, three clock sources, and one programmable periodic interrupt. This module can be used for time-of-day, calendar or any task scheduling functions. It can also serve as a cyclic wake up from low power modes without the need of external components. All devices in the MC9S08DZ128 Series feature the RTC. 15.1.
PORT A PTA7/PIA7/ADP7/IRQ PTA6/PIA6/ADP6 PTA5/PIA5/ADP5 PTA4/PIA4/ADP4 PTA3/PIA3/ADP3/ACMP1O PTA2/PIA2/ADP2/ACMP1PTA1/PIA1/ADP1/ACMP1+ PTA0/PIA0/ADP0/MCLK PORT B Chapter 15 Real-Time Counter (S08RTCV1) PTB7/PIB7/ADP15 PTB6/PIB6/ADP14 PTB5/PIB5/ADP13 PTB4/PIB4/ADP12 PTB3/PIB3/ADP11 PTB2/PIB2/ADP10 PTB1/PIB1/ADP9 PTB0/PIB0/ADP8 HCS08 CORE DEBUG MODULE (DBG) CPU BKP ANALOG COMPARATOR (ACMP1) HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT COP LVD INT IRQ VDD VSS REAL
Chapter 15 Real-Time Counter (S08RTCV1) 15.1.2 Features Features of the RTC module include: • 8-bit up-counter — 8-bit modulo match limit — Software controllable periodic interrupt on match • Three software selectable clock sources for input to prescaler with selectable binary-based and decimal-based divider values — 1-kHz internal low-power oscillator (LPO) — External clock (ERCLK) — 32-kHz internal clock (IRCLK) 15.1.
Chapter 15 Real-Time Counter (S08RTCV1) 15.1.4 Block Diagram The block diagram for the RTC module is shown in Figure 15-2. LPO Clock Source Select ERCLK IRCLK 8-Bit Modulo (RTCMOD) RTCLKS VDD RTCLKS[0] RTCPS Prescaler Divide-By Q D Background Mode E 8-Bit Comparator RTC Clock RTC Interrupt Request RTIF R Write 1 to RTIF 8-Bit Counter (RTCCNT) RTIE Figure 15-2. Real-Time Counter (RTC) Block Diagram 15.2 External Signal Description The RTC does not include any off-chip signals. 15.
Chapter 15 Real-Time Counter (S08RTCV1) 15.3.1 RTC Status and Control Register (RTCSC) RTCSC contains the real-time interrupt status flag (RTIF), the clock select bits (RTCLKS), the real-time interrupt enable bit (RTIE), and the prescaler select bits (RTCPS). 7 6 5 4 3 2 1 0 0 0 R RTIF RTCLKS RTIE RTCPS W Reset: 0 0 0 0 0 0 Figure 15-3. RTC Status and Control Register (RTCSC) Table 15-2.
Chapter 15 Real-Time Counter (S08RTCV1) 15.3.2 RTC Counter Register (RTCCNT) RTCCNT is the read-only value of the current RTC count of the 8-bit counter. 7 6 5 4 R 3 2 1 0 0 0 0 0 RTCCNT W Reset: 0 0 0 0 Figure 15-4. RTC Counter Register (RTCCNT) Table 15-4. RTCCNT Field Descriptions Field Description 7:0 RTCCNT RTC Count. These eight read-only bits contain the current value of the 8-bit counter. Writes have no effect to this register.
Chapter 15 Real-Time Counter (S08RTCV1) RTCPS and the RTCLKS[0] bit select the desired divide-by value. If a different value is written to RTCPS, the prescaler and RTCCNT counters are reset to 0x00. Table 15-6 shows different prescaler period values. Table 15-6. Prescaler Period RTCPS 1-kHz Internal Clock (RTCLKS = 00) 1-MHz External Clock 32-kHz Internal Clock 32-kHz Internal Clock (RTCLKS = 01) (RTCLKS = 10) (RTCLKS = 11) 0000 Off Off Off Off 0001 8 ms 1.024 ms 250 μs 32 ms 0010 32 ms 2.
Chapter 15 Real-Time Counter (S08RTCV1) Internal 1-kHz Clock Source RTC Clock (RTCPS = 0xA) RTCCNT 0x52 0x53 0x54 0x55 0x00 0x01 RTIF RTCMOD 0x55 Figure 15-6. RTC Counter Overflow Example In the example of Figure 15-6, the selected clock source is the 1-kHz internal oscillator clock source. The prescaler (RTCPS) is set to 0xA or divide-by-4. The modulo value in the RTCMOD register is set to 0x55.
Chapter 15 Real-Time Counter (S08RTCV1) #pragma TRAP_PROC void RTC_ISR(void) { /* Clear the interrupt flag */ RTCSC.byte = RTCSC.byte | 0x80; /* RTC interrupts every 1 Second */ Seconds++; /* 60 seconds in a minute */ if (Seconds > 59){ Minutes++; Seconds = 0; } /* 60 minutes in an hour */ if (Minutes > 59){ Hours++; Minutes = 0; } /* 24 hours in a day */ if (Hours > 23){ Days ++; Hours = 0; } MC9S08DZ128 Series Data Sheet, Rev.
Chapter 15 Real-Time Counter (S08RTCV1) MC9S08DZ128 Series Data Sheet, Rev.
Chapter 16 Timer Pulse-Width Modulator (S08TPMV3) 16.1 Introduction The TPM uses one input/output (I/O) pin per channel, TPMxCHn, where x is the TPM number (for example, 1 or 2) and n is the channel number (for example, 0–4). The TPM shares its I/O pins with general-purpose I/O port pins (refer to the Pins and Connections chapter for more information). NOTE MC9S08DZ128 Series MCUs have three TPM modules. TPM3 channels are not bonded out in the 64-pin and 48-pin packages.
PORT A PTA7/PIA7/ADP7/IRQ PTA6/PIA6/ADP6 PTA5/PIA5/ADP5 PTA4/PIA4/ADP4 PTA3/PIA3/ADP3/ACMP1O PTA2/PIA2/ADP2/ACMP1PTA1/PIA1/ADP1/ACMP1+ PTA0/PIA0/ADP0/MCLK PORT B Chapter 16 Timer Pulse-Width Modulator (S08TPMV3) PTB7/PIB7/ADP15 PTB6/PIB6/ADP14 PTB5/PIB5/ADP13 PTB4/PIB4/ADP12 PTB3/PIB3/ADP11 PTB2/PIB2/ADP10 PTB1/PIB1/ADP9 PTB0/PIB0/ADP8 HCS08 CORE DEBUG MODULE (DBG) CPU BKP ANALOG COMPARATOR (ACMP1) HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT COP LVD INT IRQ VDD
Chapter 16 Timer/PWM Module (S08TPMV3) 16.1.
Chapter 16 Timer/PWM Module (S08TPMV3) • • Edge-aligned PWM mode The value of a 16-bit modulo register plus 1 sets the period of the PWM output signal. The channel value register sets the duty cycle of the PWM output signal. The user may also choose the polarity of the PWM output signal. Interrupts are available at the end of the period and at the duty-cycle transition point.
Chapter 16 Timer/PWM Module (S08TPMV3) BUS CLOCK FIXED SYSTEM CLOCK SYNC EXTERNAL CLOCK CLOCK SOURCE SELECT OFF, BUS, FIXED SYSTEM CLOCK, EXT PRESCALE AND SELECT 1, 2, 4, 8, 16, 32, 64, or 128 CLKSB:CLKSA PS2:PS1:PS0 CPWMS 16-BIT COUNTER TOF COUNTER RESET TOIE INTERRUPT LOGIC 16-BIT COMPARATOR TPMxMODH:TPMxMODL CHANNEL 0 ELS0B ELS0A PORT LOGIC TPMxCH0 16-BIT COMPARATOR TPMxC0VH:TPMxC0VL CH0F INTERNAL BUS 16-BIT LATCH CHANNEL 1 MS0B MS0A ELS1B ELS1A CH0IE INTERRUPT LOGIC PORT LO
Chapter 16 Timer/PWM Module (S08TPMV3) The TPM channels are programmable independently as input capture, output compare, or edge-aligned PWM channels. Alternately, the TPM can be configured to produce CPWM outputs on all channels. When the TPM is configured for CPWMs, the counter operates as an up/down counter; input capture, output compare, and EPWM functions are not practical. If a channel is configured as input capture, an internal pullup device may be enabled for that channel.
Chapter 16 Timer/PWM Module (S08TPMV3) 16.2.1.1 EXTCLK — External Clock Source Control bits in the timer status and control register allow the user to select nothing (timer disable), the bus-rate clock (the normal default source), a crystal-related clock, or an external clock as the clock which drives the TPM prescaler and subsequently the 16-bit TPM counter. The external clock source is synchronized in the TPM.
Chapter 16 Timer/PWM Module (S08TPMV3) When a channel is configured for edge-aligned PWM (CPWMS=0, MSnB=1 and ELSnB:ELSnA not = 0:0), the data direction is overridden, the TPMxCHn pin is forced to be an output controlled by the TPM, and ELSnA controls the polarity of the PWM output signal on the pin. When ELSnB:ELSnA=1:0, the TPMxCHn pin is forced high at the start of each new period (TPMxCNT=0x0000), and the pin is forced low when the channel value register matches the timer counter.
Chapter 16 Timer/PWM Module (S08TPMV3) When the TPM is configured for center-aligned PWM (and ELSnB:ELSnA not = 0:0), the data direction for all channels in this TPM are overridden, the TPMxCHn pins are forced to be outputs controlled by the TPM, and the ELSnA bits control the polarity of each TPMxCHn output.
Chapter 16 Timer/PWM Module (S08TPMV3) 16.3 Register Definition This section consists of register descriptions in address order. A typical MCU system may contain multiple TPMs, and each TPM may have one to eight channels, so register names include placeholder characters to identify which TPM and which channel is being referenced. For example, TPMxCnSC refers to timer (TPM) x, channel n. TPM1C2SC would be the status and control register for channel 2 of timer 1. 16.3.
Chapter 16 Timer/PWM Module (S08TPMV3) Table 16-2. TPMxSC Field Descriptions (continued) Field Description 4–3 Clock source selects. As shown in Table 16-3, this 2-bit field is used to disable the TPM system or select one of CLKS[B:A] three clock sources to drive the counter prescaler. The fixed system clock source is only meaningful in systems with a PLL-based or FLL-based system clock. When there is no PLL or FLL, the fixed-system clock source is the same as the bus rate clock.
Chapter 16 Timer/PWM Module (S08TPMV3) Reset clears the TPM counter registers. Writing any value to TPMxCNTH or TPMxCNTL also clears the TPM counter (TPMxCNTH:TPMxCNTL) and resets the coherency mechanism, regardless of the data involved in the write. R 7 6 5 4 3 2 1 0 Bit 15 14 13 12 11 10 9 Bit 8 0 0 W Reset Any write to TPMxCNTH clears the 16-bit counter 0 0 0 0 0 0 Figure 16-8.
Chapter 16 Timer/PWM Module (S08TPMV3) When BDM is active, the coherency mechanism is frozen (unless reset by writing to TPMxSC register) such that the buffer latches remain in the state they were in when the BDM became active, even if one or both halves of the modulo register are written while BDM is active. Any write to the modulo registers bypasses the buffer latches and directly writes to the modulo register while BDM is active.
Chapter 16 Timer/PWM Module (S08TPMV3) Table 16-5. TPMxCnSC Field Descriptions Field Description 7 CHnF Channel n flag. When channel n is an input-capture channel, this read/write bit is set when an active edge occurs on the channel n pin. When channel n is an output compare or edge-aligned/center-aligned PWM channel, CHnF is set when the value in the TPM counter registers matches the value in the TPM channel n value registers.
Chapter 16 Timer/PWM Module (S08TPMV3) Table 16-6. Mode, Edge, and Level Selection CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration 0 00 01 Input capture Capture on rising edge only 01 10 Capture on falling edge only 11 Capture on rising or falling edge 01 1X Output compare 10 Clear output on compare 11 Set output on compare 10 Edge-aligned PWM X1 1 XX High-true pulses (clear output on compare) Low-true pulses (set output on compare) 10 Center-aligned PWM X1 16.3.
Chapter 16 Timer/PWM Module (S08TPMV3) (becomes unlatched) when the TPMxCnSC register is written (whether BDM mode is active or not). Any write to the channel registers will be ignored during the input capture mode. When BDM is active, the coherency mechanism is frozen (unless reset by writing to TPMxCnSC register) such that the buffer latches remain in the state they were in when the BDM became active, even if one or both halves of the channel register are read while BDM is active.
Chapter 16 Timer/PWM Module (S08TPMV3) The following sections describe the main counter and each of the timer operating modes (input capture, output compare, edge-aligned PWM, and center-aligned PWM). Because details of pin operation and interrupt activity depend upon the operating mode, these topics will be covered in the associated mode explanation sections. 16.4.1 Counter All timer functions are based on the main 16-bit counter (TPMxCNTH:TPMxCNTL).
Chapter 16 Timer/PWM Module (S08TPMV3) Table 16-7. TPM Clock Source Selection CLKSB:CLKSA TPM Clock Source to Prescaler Input 00 No clock selected (TPM counter disabled) 01 Bus rate clock 10 Fixed system clock 11 External source The bus rate clock is the main system bus clock for the MCU. This clock source requires no synchronization because it is the clock that is used for all internal MCU activities including operation of the CPU and buses.
Chapter 16 Timer/PWM Module (S08TPMV3) 16.4.1.3 Counting Modes The main timer counter has two counting modes. When center-aligned PWM is selected (CPWMS=1), the counter operates in up/down counting mode. Otherwise, the counter operates as a simple up counter. As an up counter, the timer counter counts from 0x0000 through its terminal count and then continues with 0x0000. The terminal count is 0xFFFF or a modulus value in TPMxMODH:TPMxMODL.
Chapter 16 Timer/PWM Module (S08TPMV3) In output compare mode, values are transferred to the corresponding timer channel registers only after both 8-bit halves of a 16-bit register have been written and according to the value of CLKSB:CLKSA bits, so: • If (CLKSB:CLKSA = 0:0), the registers are updated when the second byte is written • If (CLKSB:CLKSA not = 0:0), the registers are updated at the next change of the TPM counter (end of the prescaler counting) after the second byte is written.
Chapter 16 Timer/PWM Module (S08TPMV3) the TPM counter is a free-running counter then the update is made when the TPM counter changes from 0xFFFE to 0xFFFF. 16.4.2.4 Center-Aligned PWM Mode This type of PWM output uses the up/down counting mode of the timer counter (CPWMS=1). The output compare value in TPMxCnVH:TPMxCnVL determines the pulse width (duty cycle) of the PWM signal while the period is determined by the value in TPMxMODH:TPMxMODL.
Chapter 16 Timer/PWM Module (S08TPMV3) Input capture, output compare, and edge-aligned PWM functions do not make sense when the counter is operating in up/down counting mode so this implies that all active channels within a TPM must be used in CPWM mode when CPWMS=1. The TPM may be used in an 8-bit MCU. The settings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths.
Chapter 16 Timer/PWM Module (S08TPMV3) All TPM interrupts are listed in Table 16-8 which shows the interrupt name, the name of any local enable that can block the interrupt request from leaving the TPM and getting recognized by the separate interrupt processing logic. Table 16-8.
Chapter 16 Timer/PWM Module (S08TPMV3) 16.6.2.1.2 Center-Aligned PWM Case When CPWMS=1, TOF gets set when the timer counter changes direction from up-counting to down-counting at the end of the terminal count (the value in the modulo register). In this case the TOF corresponds to the end of a PWM period. 16.6.2.2 Channel Event Interrupt Description The meaning of channel interrupts depends on the channel’s current mode (input-capture, output-compare, edge-aligned PWM, or center-aligned PWM). 16.6.2.2.
Chapter 16 Timer/PWM Module (S08TPMV3) BDM mode returns the latched value of TPMxCNTH:L from the read buffer instead of the frozen TPM counter value. — This read coherency mechanism is cleared in TPM v3 in BDM mode if there is a write to TPMxSC, TPMxCNTH or TPMxCNTL. Instead, in these conditions the TPM v2 does not clear this read coherency mechanism. 3. Read of TPMxCnVH:L registers (Section 16.3.
Chapter 16 Timer/PWM Module (S08TPMV3) — TPMxCnVH:L = (TPMxMODH:L - 1) [SE110-TPM case 2] In this case, the TPM v3 produces almost 100% duty cycle. Instead, the TPM v2 produces 0% duty cycle. — TPMxCnVH:L is changed from 0x0000 to a non-zero value [SE110-TPM case 3 and 5] In this case, the TPM v3 waits for the start of a new PWM period to begin using the new duty cycle setting. Instead, the TPM v2 changes the channel output at the middle of the current PWM period (when the count reaches 0x0000).
Chapter 17 Development Support 17.1 Introduction Development support systems in the HCS08 include the background debug controller (BDC) and the on-chip debug module (DBG). The BDC provides a single-wire debug interface to the target MCU that provides a convenient interface for programming the on-chip FLASH and other nonvolatile memories.
Chapter 17 Development Support 17.1.
Chapter 17 Development Support BKGD 1 2 GND NO CONNECT 3 4 RESET NO CONNECT 5 6 VDD Figure 17-1. BDM Tool Connector 17.2.1 BKGD Pin Description BKGD is the single-wire background debug interface pin. The primary function of this pin is for bidirectional serial communication of active background mode commands and data. During reset, this pin is used to select between starting in active background mode or starting the user’s application program.
Chapter 17 Development Support when this timeout occurs is aborted without affecting the memory or operating mode of the target MCU system. The custom serial protocol requires the debug pod to know the target BDC communication clock speed. The clock switch (CLKSW) control bit in the BDC status and control register allows the user to select the BDC clock source. The BDC clock source can either be the bus or the alternate BDC clock source.
Chapter 17 Development Support Figure 17-3 shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long enough for the target to recognize it (at least two target BDC cycles).
Chapter 17 Development Support Figure 17-4 shows the host receiving a logic 0 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the target HCS08 finishes it.
Chapter 17 Development Support 17.2.3 BDC Commands BDC commands are sent serially from a host computer to the BKGD pin of the target HCS08 MCU. All commands and data are sent MSB-first using a custom BDC communications protocol. Active background mode commands require that the target MCU is currently in the active background mode while non-intrusive commands may be issued at any time whether the target MCU is in active background mode or running a user application program.
Chapter 17 Development Support Table 17-1. BDC Command Summary Command Mnemonic 1 Active BDM/ Non-intrusive Coding Structure Description SYNC Non-intrusive n/a1 Request a timed reference pulse to determine target BDC communication speed ACK_ENABLE Non-intrusive D5/d Enable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D. ACK_DISABLE Non-intrusive D6/d Disable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D.
Chapter 17 Development Support The SYNC command is unlike other BDC commands because the host does not necessarily know the correct communications speed to use for BDC communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host: • Drives the BKGD pin low for at least 128 cycles of the slowest possible BDC clock (The slowest clock is normally the reference oscillator/64 or the self-clocked rate/64.
Chapter 17 Development Support This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 17.3.1 BDC Registers and Control Bits The BDC has two registers: • The BDC status and control register (BDCSCR) is an 8-bit register containing control and status bits for the background debug controller.
Chapter 17 Development Support 17.3.1.1 BDC Status and Control Register (BDCSCR) This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL) but is not accessible to user programs because it is not located in the normal memory map of the MCU. 7 6 R 5 4 3 BKPTEN FTS CLKSW BDMACT ENBDM 2 1 0 WS WSF DVF W Normal Reset 0 0 0 0 0 0 0 0 Reset in Active BDM: 1 1 0 0 1 0 0 0 = Unimplemented or Reserved Figure 17-5.
Chapter 17 Development Support Table 17-2. BDCSCR Register Field Descriptions (continued) Field Description 2 WS Wait or Stop Status — When the target CPU is in wait or stop mode, most BDC commands cannot function. However, the BACKGROUND command can be used to force the target CPU out of wait or stop and into active background mode where all BDC commands work.
Chapter 17 Development Support R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 BDFR1 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved 1 BDFR is writable only through serial background mode debug commands, not from user programs. Figure 17-6. System Background Debug Force Reset Register (SBDFR) Table 17-3.
Chapter 17 Development Support MC9S08DZ128 Series Data Sheet, Rev.
Chapter 18 Debug Module (S08DBGV3) (128K) 18.1 Introduction The DBG module implements an on-chip ICE (in-circuit emulation) system and allows non-intrusive debug of application software by providing an on-chip trace buffer with flexible triggering capability. The trigger also can provide extended breakpoint capacity. The on-chip ICE system is optimized for the HCS08 8-bit architecture and supports 64K bytes or 128K bytes of memory space. 18.1.
Chapter 18 Debug Module (S08DBGV3) (128K) • Ability to End-trace until reset and Begin-trace from reset 18.1.2 Modes of Operation The on-chip ICE system can be enabled in all MCU functional modes. The DBG module is disabled if the MCU is secure. The DBG module comparators are disabled when executing a Background Debug Mode (BDM) command. 18.1.3 Block Diagram Figure 18-1 shows the structure of the DBG module.
Chapter 18 Debug Module (S08DBGV3) (128K) 18.3 Memory Map and Registers This section provides a detailed description of all DBG registers accessible to the end user. 18.3.1 Module Memory Map Table 18-1 shows the registers contained in the DBG module. Table 18-1.
Chapter 18 Debug Module (S08DBGV3) (128K) 18.3.2 Table 18-2.
Chapter 18 Debug Module (S08DBGV3) (128K) 18.3.3 Register Descriptions This section consists of the DBG register descriptions in address order. Note: For all registers below, consider: U = Unchanged, bit maintain its value after reset. 18.3.3.1 Debug Comparator A High Register (DBGCAH) Module Base + 0x0000 7 6 5 4 3 2 1 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 POR or nonend-run 1 1 1 1 1 1 1 1 Reset end-run1 U U U U U U U U R W Figure 18-2.
Chapter 18 Debug Module (S08DBGV3) (128K) Table 18-4. DBGCAL Field Descriptions Field Description Bits 7–0 Comparator A Low Compare Bits — The Comparator A Low compare bits control whether Comparator A will compare the address bus bits [7:0] to a logic 1 or logic 0. 0 Compare corresponding address bit to a logic 0 1 Compare corresponding address bit to a logic 1 18.3.3.
Chapter 18 Debug Module (S08DBGV3) (128K) 1 In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset. Table 18-6. DBGCBL Field Descriptions Field Description Bits 7–0 Comparator B Low Compare Bits — The Comparator B Low compare bits control whether Comparator B will compare the address bus or data bus bits [7:0] to a logic 1 or logic 0.
Chapter 18 Debug Module (S08DBGV3) (128K) 18.3.3.6 Debug Comparator C Low Register (DBGCCL) Module Base + 0x0005 7 6 5 4 3 2 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR or nonend-run 0 0 0 0 0 0 0 0 Reset end-run1 U U U U U U U U R W Figure 18-7. Debug Comparator C Low Register (DBGCCL) 1 In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset. Table 18-8.
Chapter 18 Debug Module (S08DBGV3) (128K) Table 18-9. DBGFH Field Descriptions Field Description Bits 15–8 FIFO High Data Bits — The FIFO High data bits provide access to bits [15:8] of data in the FIFO. This register is not used in event only modes and will read a $00 for valid FIFO words. 18.3.3.
Chapter 18 Debug Module (S08DBGV3) (128K) 18.3.3.9 Debug Comparator A Extension Register (DBGCAX) Module Base + 0x0008 7 6 5 RWAEN RWA PAGSEL POR or nonend-run 0 0 0 0 0 0 0 0 Reset end-run1 U U U 0 0 0 0 U R 4 3 2 1 0 0 0 0 0 Bit 16 W = Unimplemented or Reserved Figure 18-10. Debug Comparator A Extension Register (DBGCAX) 1 In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset. Table 18-11.
Chapter 18 Debug Module (S08DBGV3) (128K) 18.3.3.10 Debug Comparator B Extension Register (DBGCBX) Module Base + 0x0009 7 6 5 RWBEN RWB PAGSEL POR or nonend-run 0 0 0 0 0 0 0 0 Reset end-run1 U U U 0 0 0 0 U R 4 3 2 1 0 0 0 0 0 Bit 16 W = Unimplemented or Reserved Figure 18-11. Debug Comparator B Extension Register (DBGCBX) 1 In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset. Table 18-12.
Chapter 18 Debug Module (S08DBGV3) (128K) 18.3.3.11 Debug Comparator C Extension Register (DBGCCX) Module Base + 0x000A 7 6 5 RWCEN RWC PAGSEL POR or nonend-run 0 0 0 0 0 0 0 0 Reset end-run1 U U U 0 0 0 0 U R 4 3 2 1 0 0 0 0 0 Bit 16 W = Unimplemented or Reserved Figure 18-12. Debug Comparator C Extension Register (DBGCCX) 1 In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset. Table 18-13.
Chapter 18 Debug Module (S08DBGV3) (128K) 18.3.3.12 Debug FIFO Extended Information Register (DBGFX) Module Base + 0x000B 7 6 5 4 3 2 1 0 PPACC 0 0 0 0 0 0 Bit 16 POR or nonend-run 0 0 0 0 0 0 0 0 Reset end-run1 U 0 0 0 0 0 0 U R W = Unimplemented or Reserved Figure 18-13. Debug FIFO Extended Information Register (DBGFX) 1 In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset. Table 18-14.
Chapter 18 Debug Module (S08DBGV3) (128K) 18.3.3.13 Debug Control Register (DBGC) Module Base + 0x000C 7 6 5 4 DBGEN ARM TAG BRKEN POR or nonend-run 1 1 0 0 0 0 0 0 Reset end-run1 U 0 U 0 0 0 0 U R 3 2 1 0 0 0 0 LOOP1 W = Unimplemented or Reserved Figure 18-14. Debug Control Register (DBGC) 1 In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the ARM and BRKEN bits are cleared but the remaining control bits in this register do not change after reset.
Chapter 18 Debug Module (S08DBGV3) (128K) 18.3.3.14 Debug Trigger Register (DBGT) Module Base + 0x000D 7 6 TRGSEL BEGIN POR or nonend-run 0 1 0 0 0 Reset end-run1 U U 0 0 U R W2 5 4 0 0 3 2 1 0 0 0 0 U U U TRG = Unimplemented or Reserved Figure 18-15. Debug Trigger Register (DBGT) 1 2 In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the control bits in this register do not change after reset. The DBG trigger register (DBGT) can not be changed unless ARM=0.
Chapter 18 Debug Module (S08DBGV3) (128K) Table 18-17. Trigger Mode Encoding TRG Value Meaning 1001 ↓ 1111 No Trigger NOTE The DBG trigger register (DBGT) can not be changed unless ARM=0. 18.3.3.15 Debug Status Register (DBGS) Module Base + 0x000E 7 6 5 4 3 2 1 0 AF BF CF 0 0 0 0 ARMF POR or nonend-run 0 0 0 0 0 0 0 1 Reset end-run1 U U U 0 0 0 0 0 R W = Unimplemented or Reserved Figure 18-16.
Chapter 18 Debug Module (S08DBGV3) (128K) 18.3.3.16 Debug Count Status Register (DBGCNT) Module Base + 0x000F 7 6 5 4 0 0 0 0 POR or nonend-run 0 0 0 0 0 Reset end-run1 0 0 0 0 U R 3 2 1 0 0 0 0 U U U CNT W = Unimplemented or Reserved Figure 18-17. Debug Count Status Register (DBGCNT) 1 In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the CNT[3:0] bits do not change after reset. Table 18-19.
Chapter 18 Debug Module (S08DBGV3) (128K) 18.4 Functional Description This section provides a complete functional description of the on-chip ICE system. The DBG module is enabled by setting the DBGEN bit in the DBGC register. Enabling the module allows the arming, triggering and storing of data in the FIFO. The DBG module is made up of three main blocks, the Comparators, Trigger Break Control logic and the FIFO. 18.4.1 Comparator The DBG module contains three comparators, A, B, and C.
Chapter 18 Debug Module (S08DBGV3) (128K) 18.4.2 Breakpoints A breakpoint request to the CPU at the end of a trace run can be created if the BRKEN bit in the DBGC register is set. The value of the BEGIN bit in DBGT register determines when the breakpoint request to the CPU will occur. If the BEGIN bit is set, begin-trigger is selected and the breakpoint request will not occur until the FIFO is filled with 8 words.
Chapter 18 Debug Module (S08DBGV3) (128K) 18.4.4 Trigger Break Control (TBC) The TBC is the main controller for the DBG module. Its function is to decide whether data should be stored in the FIFO based on the trigger mode and the match signals from the comparator. The TBC also determines whether a request to break the CPU should occur. The TAG bit in DBGC controls whether CPU breakpoints are treated as tag-type or force-type breakpoints.
Chapter 18 Debug Module (S08DBGV3) (128K) end the trace run that was in progress. The ARMF bit is also cleared if ARM is written to zero or when the DBGEN bit is low. The TBC logic determines whether a trigger condition has been met based on the trigger mode and the trigger selection. 18.4.4.3 Trigger Modes The on-chip ICE system supports nine trigger modes. The trigger modes are encoded as shown in Table 18-17.
Chapter 18 Debug Module (S08DBGV3) (128K) 18.4.4.3.7 A And Not B (Full Mode) In the A And Not B trigger mode, comparator A compares to the address bus and comparator B compares to the data bus. In the A And Not B trigger mode, if the match condition for A and Not B happen on the same bus cycle, both the AF and BF flags in the DBGS register are set. If a match condition on only A or only Not B occur no flags are set.
Chapter 18 Debug Module (S08DBGV3) (128K) 1 When BRKEN = 0, TAG is do not care (x in the table). 2 In end trace configurations (BEGIN = 0) where a CPU breakpoint is enabled (BRKEN = 1), TRGSEL should agree with TAG. In this case, where TRGSEL = 0 to select no opcode tracking qualification and TAG = 1 to specify a tag-type CPU breakpoint, the CPU breakpoint would not take effect until sometime after the FIFO stopped storing values. Depending on program loops or interrupts, the delay could be very long.
Chapter 18 Debug Module (S08DBGV3) (128K) in the DBGCNT register at the end of a trace run, the number of valid words can be determined. The FIFO data is read by optionally reading the DBGFX and DBGFH registers followed by the DBGFL register. Each time the DBGFL register is read the FIFO is shifted to allow reading of the next word however the count does not decrement. In event-only trigger modes where the FIFO will contain only the data bus values stored, to read the FIFO only DBGFL needs to be accessed.
Chapter 18 Debug Module (S08DBGV3) (128K) • • • 18.6 DBGCAX=0x00, DBGCAH=0xFF, DBGCAL=0xFE so comparator A is set to match when the 16-bit CPU address 0xFFFE appears during the reset vector fetch DBGC=0xC0 to enable and arm the DBG module DBGT=0x40 to select a force-type trigger, a BEGIN trigger, and A-only trigger mode Interrupts The DBG contains no interrupt source. 18.7 Electrical Specifications The DBG module contain no electrical specifications. MC9S08DZ128 Series Data Sheet, Rev.
Chapter 18 Debug Module (S08DBGV3) (128K) MC9S08DZ128 Series Data Sheet, Rev.
Appendix A Electrical Characteristics A.1 Introduction This section contains the most accurate electrical and timing information for the MC9S08DZ128 Series of microcontrollers available at the time of publication. A.2 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate: Table A-1.
Appendix A Electrical Characteristics maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD). y Table A-2. Absolute Maximum Ratings Num Rating Symbol Value Unit 1 Supply voltage VDD –0.3 to + 5.8 V 2 Input voltage VIn – 0.3 to VDD + 0.
Appendix A Electrical Characteristics Table A-3.
Appendix A Electrical Characteristics where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations 1 and 2 iteratively for any value of TA. A.
Appendix A Electrical Characteristics A.6 DC Characteristics This section includes information about power supply requirements, I/O pin characteristics, and power supply current in various operating modes. Table A-6. DC Characteristics Num C 1 2 3 4 5 6 7 Characteristic Symbol Max Unit V 2.7 — 5.5 5 V, ILoad = –4 mA VDD – 1.5 — — P low-drive strength 5 V, ILoad = –2 mA VDD – 0.8 — — 3 V, ILoad = –1 mA VDD – 0.8 — — 5 V, ILoad = –20 mA VDD – 1.
Appendix A Electrical Characteristics Table A-6. DC Characteristics (continued) Num C 14 15 Characteristic Min Typ1 Max Unit VRAM — 0.6 1.0 V VPOR 0.9 1.4 2.0 V tPOR 10 — — μs 3.9 4.0 4.0 4.1 4.1 4.2 V 2.48 2.54 2.56 2.62 2.64 2.70 V 4.5 4.6 4.6 4.7 4.7 4.8 V 4.2 4.3 4.3 4.4 4.4 4.5 V 2.84 2.90 2.92 2.98 3.00 3.06 V 2.66 2.72 2.74 2.80 2.82 2.88 V 5V — 100 — 3V — 60 — 1.19 1.20 1.
Appendix A Electrical Characteristics 2 1.0 125˚C 25˚C –40˚C 0.8 VOL (V) VOL (V) 1.5 1 0.5 0 125˚C 25˚C –40˚C Max 1.5V@25mA Max 0.8V@5mA 0.6 0.4 0.2 0 5 10 15 IOL (mA) a) VDD = 5V, High Drive 20 0 25 0 2 4 6 IOL (mA) b) VDD = 3V, High Drive 8 10 Figure A-1. Typical VOL vs IOL, High Drive Strength 2 1.0 125˚C 25˚C –40˚C 0.8 VOL (V) VOL (V) 1.5 1 0.5 0 125˚C 25˚C –40˚C Max 1.5V@4mA Max 0.8V@1mA 0.6 0.4 0.2 0 1 2 3 IOL (mA) a) VDD = 5V, Low Drive 4 5 0 0 0.4 0.8 1.
Appendix A Electrical Characteristics 2 1.0 125˚C 25˚C –40˚C 0.8 VDD – VOH (V) VDD – VOH (V) 1.5 1 0.5 0 125˚C 25˚C –40˚C Max 1.5V@20mA Max 0.8V@5mA 0.6 0.4 0.2 0 –5 –10 –15 –20 IOH (mA) a) VDD = 5V, High Drive 0 –25 0 –2 –4 –6 –8 IOH (mA) b) VDD = 3V, High Drive –10 Figure A-3. Typical VDD – VOH vs IOH, High Drive Strength 2 1.0 125˚C 25˚C –40˚C 0.8 VDD – VOH (V) VDD – VOH (V) 1.5 1 0.5 0 125˚C 25˚C –40˚C Max 1.5V@4mA Max 0.8V@1mA 0.6 0.4 0.
Appendix A Electrical Characteristics A.7 Supply Current Characteristics This section includes information about power supply current in various operating modes. Table A-7. Supply Current Characteristics Num C C 1 2 C C C P 3 C Parameter Symbol 3 Run supply current measured at (CPU clock = 2 MHz, fBus = 1 MHz) RIDD Run supply current3 measured at (CPU clock = 16 MHz, fBus = 8 MHz) RIDD 4 Run supply current measured at (CPU clock = 40 MHz, fBus = 20MHz) RIDD VDD (V) Typ1 Max2 5 2.
Appendix A Electrical Characteristics Table A-7. Supply Current Characteristics (continued) Num C 8 P P 1 2 3 4 5 6 7 Parameter Adder to stop3 for oscillator enabled7 (EREFSTEN =1) Symbol S3IDDOSC VDD (V) Typ1 Max2 5 5 8 3 5 8 Unit μA Typical are measured at 25°C. See Figure A-8 through Figure A-10 for typical curves across voltage/temperature. Max values in this column apply for the full operating temperature range of the device unless otherwise noted.
Appendix A Electrical Characteristics 20 fbus = 20MHz 18 16 Run IDD (mA) 14 12 fbus = 8MHz 10 8 6 4 2 0 –40 0 25 Temperature (˚C) 85 125 105 Figure A-6. Typical Run IDD vs. Temperature (VDD = 5V) STOP IDD (μA) 150 140 130 120 110 100 90 80 70 60 50 STOP2 STOP3 40 30 20 10 0 –40 0 25 Temperature (˚C) 85 105 125 Figure A-7. Typical Stop IDD vs. Temperature (VDD = 5V) A.8 Analog Comparator (ACMP) Electricals Table A-8.
Appendix A Electrical Characteristics Table A-8. Analog Comparator Electrical Specifications Num C 2 D 3 Rating Symbol Min Typical Max Unit Supply current (active) IDDAC — 20 35 μA D Analog input voltage VAIN VSS – 0.3 — VDD V 4 D Analog input offset voltage VAIO 20 40 mV 5 D Analog Comparator hysteresis 6 D 7 D VH 3.0 6.0 20.0 mV Analog input leakage current IALKG -- -- 1.0 μA Analog Comparator initialization delay tAINIT — — 1.
Appendix A Electrical Characteristics A.9 ADC Characteristics Table A-9. 5 Volt 12-bit ADC Operating Conditions Symb Min Typ1 Max Unit Absolute VDDA 2.7 — 5.5 V Delta to VDD (VDD-VDDA)2 ΔVDDA -100 0 +100 mV Delta to VSS (VSS-VSSA)2 ΔVSSA -100 0 +100 mV Ref Voltage High VREFH 2.7 VDDA VDDA V • Applicable only in 100-pin and 64-pin packages. Ref Voltage Low VREFL VSSA VSSA VSSA V • Applicable only in 100-pin and 64-pin packages.
Appendix A Electrical Characteristics SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN Pad leakage due to input protection ZAS RAS SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN ADC SAR ENGINE + VADIN VAS + – CAS – RADIN INPUT PIN INPUT PIN RADIN RADIN INPUT PIN CADIN Figure A-8. ADC Input Impedance Equivalency Diagram MC9S08DZ128 Series Data Sheet, Rev.
Appendix A Electrical Characteristics Table A-10. 5 Volt 12-bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) Characteristic Conditions C Supply Current ADLPC=1 ADLSMP=1 ADCO=1 Symb Min Typ1 Max Unit IDDAD — 133 — μA IDDAD — 218 — μA IDDAD — 327 — μA IDDAD — 0.582 1 mA IDDAD — 0.011 1 μA fADACK 2 3.3 5 MHz 1.25 2 3.3 tADACK = 1/fADACK — 20 — — 40 — ADCK cycles — 3.5 — See the ADC Chapter for conversion time variances — 23.5 — — ±3.
Appendix A Electrical Characteristics Table A-10. 5 Volt 12-bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued) C Symb Min Typ1 Max Unit Comment 12 bit mode T EFS — ±1 ±4.0 LSB2 VADIN = VDDAD 10 bit mode T — ±0.5 ±1 8 bit mode T — ±0.5 ±0.5 12 bit mode D — -1 to 0 -1 to 0 10 bit mode — — ±0.5 8 bit mode — — ±0.5 — ±1 ±10.0 10 bit mode — ±0.2 ±2.5 8 bit mode — ±0.1 ±1 — 3.266 — — 3.638 — — 1.
Appendix A Electrical Characteristics A.10 External Oscillator (XOSC) Characteristics Table A-11. Oscillator Electrical Specifications (Temperature Range = –40 to 125°C Ambient) Num C Rating Symbol Min Typ1 Max Unit Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1) flo 32 — 38.
Appendix A Electrical Characteristics MCU EXTAL XTAL RS RF C1 A.11 Crystal or Resonator C2 MCG Specifications Table A-12. MCG Frequency Specifications (Temperature Range = –40 to 125°C Ambient) Num C Rating Symbol Min Typical Max Unit 1 Internal reference frequency - factory trimmed at P VDD=5.0V and temperature=25C fint_ft — 31.25 — kHz 2 P Internal reference frequency - untrimmed 1 fint_ut 25 36 41.66 kHz 3 P Internal reference frequency - user trimmed fint_t 31.25 — 39.
Appendix A Electrical Characteristics Table A-12. MCG Frequency Specifications (Temperature Range = –40 to 125°C Ambient) (continued) Num C 1 2 3 4 5 6 7 8 9 Rating Symbol Min Typical Max Unit fpll_ref 1.0 — 2.0 MHz 15 D PLL reference frequency range 16 T RMS frequency variation of a single clock cycle measured 2 ms after reference edge.6 fpll_cycjit_2ms — 0.5905 — %fpll 17 T Maximum frequency variation averaged over 2 ms window. fpll_maxjit_2ms — 0.
Deviation from Trimmed Frequency Appendix A Electrical Characteristics +2% +1% 0 –1% –2% –40 0 25 Temperature (˚C) 85 105 125 Figure A-9. Typical Frequency Deviation vs Temperature (ICS Trimmed to 16MHz bus@25˚C, 5V, FEI)1 A.12 AC Characteristics This section describes ac timing characteristics for each peripheral system. A.12.1 Control Timing Table A-13.
Appendix A Electrical Characteristics 3 When any reset is initiated, internal circuitry drives the RESET pin low for about 34 cycles of fsys. After POR reset, the bus clock frequency changes to the untrimmed DCO frequency (freset = (fdco_ut)/4) because TRIM is reset to 0x80, FTRIM is reset to 0, and there is an extra divide-by-two because BDIV is reset to 0:1. After other resets, trim stays at the pre-reset value. 4 Timing is shown with respect to 20% VDD and 80% VDD levels.
Appendix A Electrical Characteristics A.12.2 Timer/PWM Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table A-14. TPM Input Timing Num C 1 — 2 Rating Symbol Min Max Unit External clock frequency fTPMext dc fBus/4 MHz — External clock period tTPMext 4 — tcyc 3 D External clock high time tclkh 1.
Appendix A Electrical Characteristics A.12.3 MSCAN Table A-15. MSCAN Wake-up Pulse Characteristics Num C Rating Symbol Min Typ Max Unit 1 D MSCAN Wake-up dominant pulse filtered tWUP — — 2 μs 2 D MSCAN Wake-up dominant pulse pass tWUP 5 — — μs MC9S08DZ128 Series Data Sheet, Rev.
Appendix A Electrical Characteristics A.12.4 SPI Table A-16 and Figure A-15 through Figure A-18 describe the timing requirements for the SPI system. Table A-16. SPI Electrical Characteristic Num1 C 1 D Rating2 Symbol Min Max Unit Master Slave tSCK tSCK 2 2.
Appendix A Electrical Characteristics SS1 (OUTPUT) 1 2 SCK (CPOL = 0) (OUTPUT) 3 5 4 SCK (CPOL = 1) (OUTPUT) 5 4 6 MISO (INPUT) 7 MSB IN2 BIT 6 . . . 1 10 MOSI (OUTPUT) LSB IN 10 MSB OUT2 11 BIT 6 . . . 1 LSB OUT NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure A-15.
Appendix A Electrical Characteristics SS (INPUT) 3 1 SCK (CPOL = 0) (INPUT) 5 4 2 SCK (CPOL = 1) (INPUT) 5 4 8 MISO (OUTPUT) 11 10 BIT 6 . . . 1 MSB OUT SLAVE SEE NOTE SLAVE LSB OUT 7 6 MOSI (INPUT) 9 BIT 6 . . . 1 MSB IN LSB IN NOTE: 1. Not defined but normally MSB of character just received Figure A-17. SPI Slave Timing (CPHA = 0) SS (INPUT) 1 3 2 SCK (CPOL = 0) (INPUT) 5 4 SCK (CPOL = 1) (INPUT) 5 4 10 MISO (OUTPUT) SEE NOTE 8 MOSI (INPUT) SLAVE 11 MSB OUT 6 BIT 6 . . .
Appendix A Electrical Characteristics A.13 FLASH and EEPROM This section provides details about program/erase times and program-erase endurance for the FLASH and EEPROM memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see Chapter 4, “Memory.” NOTE All values shown in Table A-17 are preliminary and subject to further characterization. Table A-17.
Appendix A Electrical Characteristics A.14 EMC Performance Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance.
Appendix B Ordering Information and Mechanical Drawings B.1 Ordering Information This section contains ordering information for MC9S08DZ128 Series devices. Example of the device numbering system: MC 9 S08 DZ 128 F2 C xx Status - S = Auto Qualified - MC = Fully Qualified Package Designator Two letter descriptor (refer to Table B-2).
Appendix B Ordering Information and Mechanical Drawings B.2 Mechanical Drawings The following pages are mechanical drawings for the packages described in the following table: Table B-2. Package Descriptions Pin Count Type Abbreviation Designator Document No. 100 Low-profile Quad Flat Package LQFP LL 98ASS23308W 64 Low-profile Quad Flat Package LQFP LH 98ASS23234W 48 Low-profile Quad Flat Package LQFP LF 98ASH00962A MC9S08DZ128 Series Data Sheet, Rev.
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