Datasheet

Chapter 6 Parallel Input/Output Control
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor 129
6.5.8 Port H Registers
Port H is controlled by the registers listed below.
6.5.8.1 Port H Data Register (PTHD)
6.5.8.2 Port H Data Direction Register (PTHDD)
76543210
R
PTHD7 PTHD6 PTHD5 PTHD4 PTHD3 PTHD2 PTHD1 PTHD0
W
Reset: 00000000
Figure 6-47. Port H Data Register (PTHD)
Table 6-45. PTHD Register Field Descriptions
Field Description
7:0
PTHD[7:0]
Port H Data Register Bits — For port H pins that are inputs, reads return the logic level on the pin. For port H
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port H pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTHD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pull-ups disabled.
76543210
R
PTHDD7 PTHDD6 PTHDD5 PTHDD4 PTHDD3 PTHDD2 PTHDD1 PTHDD0
W
Reset: 00000000
Figure 6-48. Port H Data Direction Register (PTHDD)
Table 6-46. PTHDD Register Field Descriptions
Field Description
7:0
PTHDD[7:0]
Data Direction for Port H Bits — These read/write bits control the direction of port H pins and what is read for
PTHD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port H bit n and PTHD reads return the contents of PTHDn.