Datasheet

Chapter 6 Parallel Input/Output Control
MC9S08DZ128 Series Data Sheet, Rev. 1
132 Freescale Semiconductor
6.5.9 Port J Registers
Port J is controlled by the registers listed below.
6.5.9.1 Port J Data Register (PTJD)
6.5.9.2 Port J Data Direction Register (PTJDD)
76543210
R
PTJD7 PTJD6 PTJD5 PTJD4 PTJD3 PTJD2 PTJD1 PTJD0
W
Reset: 00000000
Figure 6-52. Port J Data Register (PTJD)
Table 6-50. PTJD Register Field Descriptions
Field Description
7:0
PTJD[7:0]
Port J Data Register Bits — For port J pins that are inputs, reads return the logic level on the pin. For port J
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port J pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTJD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups disabled.
76543210
R
PTJDD7 PTJDD6 PTJDD5 PTJDD4 PTJDD3 PTJDD2 PTJDD1 PTJDD0
W
Reset: 00000000
Figure 6-53. Port J Data Direction Register (PTJDD)
Table 6-51. PTJDD Register Field Descriptions
Field Description
7:0
PTJDD[7:0]
Data Direction for Port J Bits — These read/write bits control the direction of port J pins and what is read for
PTJD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port J bit n and PTJD reads return the contents of PTJDn.