Datasheet

Chapter 6 Parallel Input/Output Control
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor 139
6.5.11 Port L Registers
Port L is controlled by the registers listed below.
6.5.11.1 Port L Data Register (PTLD)
6.5.11.2 Port L Data Direction Register (PTLDD)
76543210
R
PTLD7 PTLD6 PTLD5 PTLD4 PTLD3 PTLD2 PTLD1 PTLD0
W
Reset: 00000000
Figure 6-65. Port L Data Register (PTLD)
Table 6-63. PTLD Register Field Descriptions
Field Description
7:0
PTLD[7:0]
Port L Data Register Bits — For port L pins that are inputs, reads return the logic level on the pin. For port L
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port L pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTLD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups disabled.
76543210
R
PTLDD7 PTLDD6 PTLDD5 PTLDD4 PTLDD3 PTLDD2 PTLDD1 PTLDD0
W
Reset: 00000000
Figure 6-66. Port L Data Direction Register (PTLDD)
Table 6-64. PTLDD Register Field Descriptions
Field Description
7:0
PTLDD[7:0]
Data Direction for Port L Bits — These read/write bits control the direction of port L pins and what is read for
PTLD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port L bit n and PTLD reads return the contents of PTLDn.