Datasheet

Chapter 6 Parallel Input/Output Control
MC9S08DZ128 Series Data Sheet, Rev. 1
140 Freescale Semiconductor
6.5.11.3 Port L Pull Enable Register (PTLPE)
NOTE
Pull-down devices only apply when using pin interrupt functions, when
corresponding edge select and pin select functions are configured.
6.5.11.4 Port L Slew Rate Enable Register (PTLSE)
Note: Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew
rate control to the desired value to ensure correct operation.
76543210
R
PTLPE7 PTLPE6 PTLPE5 PTLPE4 PTLPE3 PTLPE2 PTLPE1 PTLPE0
W
Reset: 00000000
Figure 6-67. Internal Pull Enable for Port L Register (PTLPE)
Table 6-65. PTLPE Register Field Descriptions
Field Description
7:0
PTLPE[7:0]
Internal Pull Enable for Port L Bits — Each of these control bits determines if the internal pull-up device is
enabled for the associated PTL pin. For port L pins that are configured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port L bit n.
1 Internal pull-up device enabled for port L bit n.
76543210
R
PTLSE7 PTLSE6 PTLSE5 PTLSE4 PTLSE3 PTLSE2 PTLSE1 PTLSE0
W
Reset: 00000000
Figure 6-68. Slew Rate Enable for Port L Register (PTLSE)
Table 6-66. PTLSE Register Field Descriptions
Field Description
7:0
PTLSE[7:0]
Output Slew Rate Enable for Port L Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTL pin. For port L pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port L bit n.
1 Output slew rate control enabled for port L bit n.