Datasheet

Chapter 8 Multi-Purpose Clock Generator (S08MCGV2)
MC9S08DZ128 Series Data Sheet, Rev. 1
192 Freescale Semiconductor
– IREFS (bit 2) set to 1 to select the internal reference clock as the reference clock source
– RDIV (bits 5-3) remain unchanged because the reference divider does not affect the internal
reference.
b) Loop until IREFST (bit 4) in MCGSC is 1, indicating the internal reference clock has been
selected as the reference clock source
c) Loop until CLKST (bits 3 and 2) in MCGSC are %01, indicating that the internal reference
clock is selected to feed MCGOUT
4. Lastly, FBI transitions into BLPI mode.
a) MCGC2 = 0x08 (%00001000)
– LP (bit 3) in MCGSC is 1
– RANGE, HGO, EREFS, ERCLKEN, and EREFSTEN bits are ignored when the IREFS bit
(bit2) in MCGC is set. They can remain set, or be cleared at this point.