Datasheet

Chapter 18 Debug Module (S08DBGV3) (128K)
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor 397
18.3.3 Register Descriptions
This section consists of the DBG register descriptions in address order.
Note: For all registers below, consider: U = Unchanged, bit maintain its value after reset.
18.3.3.1 Debug Comparator A High Register (DBGCAH)
18.3.3.2 Debug Comparator A Low Register (DBGCAL)
Module Base + 0x0000
76543210
R
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
POR
or non-
end-run
11111111
Reset
end-run
1
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
UUUUUUUU
Figure 18-2. Debug Comparator A High Register (DBGCAH)
Table 18-3. DBGCAH Field Descriptions
Field Description
Bits 15–8 Comparator A High Compare Bits — The Comparator A High compare bits control whether Comparator A will
compare the address bus bits [15:8] to a logic 1 or logic 0.
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
Module Base + 0x0001
76543210
R
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
POR
or non-
end-run
11111110
Reset
end-run
1
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
UUUUUUUU
Figure 18-3. Debug Comparator A Low Register (DBGCAL)