Datasheet

Chapter 18 Debug Module (S08DBGV3) (128K)
MC9S08DZ128 Series Data Sheet, Rev. 1
400 Freescale Semiconductor
18.3.3.6 Debug Comparator C Low Register (DBGCCL)
18.3.3.7 Debug FIFO High Register (DBGFH)
Module Base + 0x0005
76543210
R
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
POR
or non-
end-run
00000000
Reset
end-run
1
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
UUUUUUUU
Figure 18-7. Debug Comparator C Low Register (DBGCCL)
Table 18-8. DBGCCL Field Descriptions
Field Description
Bits 7–0 Comparator C Low Compare Bits — The Comparator C Low compare bits control whether Comparator C will
compare the address bus bits [7:0] to a logic 1 or logic 0.
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
Module Base + 0x0006
76543210
R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
POR
or non-
end-run
00000000
Reset
end-run
1
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
UUUUUUUU
= Unimplemented or Reserved
Figure 18-8. Debug FIFO High Register (DBGFH)