Datasheet

Chapter 18 Debug Module (S08DBGV3) (128K)
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor 405
18.3.3.12 Debug FIFO Extended Information Register (DBGFX)
Module Base + 0x000B
76543210
R PPACC 0 0 0 0 0 0 Bit 16
W
POR
or non-
end-run
00000000
Reset
end-run
1
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
U000000U
= Unimplemented or Reserved
Figure 18-13. Debug FIFO Extended Information Register (DBGFX)
Table 18-14. DBGFX Field Descriptions
Field Description
7
PPACC
PPAGE Access Indicator Bit — This bit indicates whether the captured information in the current FIFO word is
associated with an extended access through the PPAGE mechanism or not. This is indicated by the internal
signal mmu_ppage_sel which is 1 when the access is through the PPAGE mechanism.
0 The information in the corresponding FIFO word is event-only data or an unpaged 17-bit CPU address with
bit-16 = 0
1 The information in the corresponding FIFO word is a 17-bit flash address with PPAGE[2:0] in the three most
significant bits and CPU address[13:0] in the 14 least significant bits
0
Bit 16
Extended Address Bit 16 — This bit is the most significant bit of the 17-bit core address.