Datasheet

Appendix A Electrical Characteristics
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor 437
15 D PLL reference frequency range
f
pll_ref
1.0 — 2.0 MHz
16 T
RMS frequency variation of a single clock cycle measured
2 ms after reference edge.
6
f
pll_cycjit_2ms
—
0.590
5
—
%f
pll
17 T
Maximum frequency variation averaged over 2 ms
window.
f
pll_maxjit_2ms
— 0.001 —
%f
pll
18 T
RMS frequency variation of a single clock cycle measured
625 ns after reference edge.
7
f
pll_cycjit_625ns
—
0.566
5
—
%f
pll
19 T
Maximum frequency variation averaged over 625 ns
window.
f
pll_maxjit_625ns
— 0.113 —
%f
pll
20 D
Lock entry frequency tolerance
8
D
lock
± 1.49 — ± 2.98 %
21 D
Lock exit frequency tolerance
9
D
unl
± 4.47 — ± 5.97 %
22 D Lock time - FLL
t
fll_lock
——
t
fll_acquire+
1075(1/
f
int_t)
s
1
This applies when TRIM register at value (0x80) and FTRIM control bit at value (0x0). These values load when in BDM modes.
2
The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.
3
This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit
is changed, DRS bit is changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a
crystal/resonator is being used as the reference, this specification assumes it is already running.
4
This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE,
BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already
running.
5
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
BUS
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected
into the FLL circuitry via V
DD
and V
SS
and variation in crystal oscillator frequency increase the C
Jitter
percentage for a given interval.
These jitter measurements are based upon a 40 MHz MCGOUT clock frequency.
6
In some specifications, this value is described as, “Long term accuracy of PLL output clock (averaged over 2 ms)” with symbol
“f
pll_jitter_2ms
.” The parameter is unchanged, but the description has been changed for clarification purposes.
7
In some specifications, this value is described as “Jitter of PLL output clock measured over 625 ns” with symbol “f
pll_jitter_625ns
.”
The parameter is unchanged, but the description has been changed for clarification purposes.
8
Below D
lock
minimum, the MCG is guaranteed to enter lock. Above D
lock
maximum, the MCG will not enter lock. But if the MCG is
already in lock, then the MCG may stay in lock.
9
Below D
unl
minimum, the MCG will not exit lock if already in lock. Above D
unl
maximum, the MCG is guaranteed to exit lock.
Table A-12. MCG Frequency Specifications (Temperature Range = –40 to 125°C Ambient) (continued)
Num C Rating Symbol Min Typical Max Unit