Datasheet

Appendix A Electrical Characteristics
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor 439
Figure A-10. Reset Timing
Figure A-11. Active Background Debug Mode Latch Timing
Figure A-12. Pin Interrupt Timing
3
When any reset is initiated, internal circuitry drives the RESET pin low for about 34 cycles of f
sys
. After POR reset, the bus
clock frequency changes to the untrimmed DCO frequency (f
reset
=(f
dco_ut
)/4) because TRIM is reset to 0x80, FTRIM is reset
to 0, and there is an extra divide-by-two because BDIV is reset to 0:1. After other resets, trim stays at the pre-reset value.
4
Timing is shown with respect to 20% V
DD
and 80% V
DD
levels. Temperature range –40°C to 125°C.
t
extrst
RESET PIN
BKGD/MS
RESET
t
MSSU
t
MSH
t
IHIL
PIAx/PIBx/PIDx/PIJx
t
ILIH
Q
/PIAx/PIBx/PIDx/PIJx