Datasheet

Chapter 4 Memory
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor 59
Figure 4-4 shows the structure of receive and transmit buffers for extended identifier mapping. These
registers vary depending on whether standard or extended mapping is selected. See Chapter 12,
“Freescale’s Controller Area Network (S08MSCANV1),” for details on extended and standard identifier
mapping.
0x18C7 TPM3C0VL
Bit 7 654321Bit 0
0x18C8 TPM3C1SC
CH1F CH1IE MS1B MS1A ELS1B ELS1A 0 0
0x18C9 TPM3C1VH
Bit 15 14 13 12 11 10 9 Bit 8
0x18CA TPM3C1VL
Bit 7 654321Bit 0
0x18CB TPM3C2SC
CH2F CH2IE MS2B MS2A ELS2B ELS2A 0 0
0x18CC TPM3C2VH
Bit 15 14 13 12 11 10 9 Bit 8
0x18CD TPM3C2VL
Bit 7 654321Bit 0
0x18CE TPM3C3SC
CH3F CH3IE MS3B MS3A ELS3B ELS3A 0 0
0x18CF TPM3C3VH
Bit 15 14 13 12 11 10 9 Bit 8
0x18D0 TPM3C3VL
Bit 7 654321Bit 0
0x18D1–
0x18D7
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x18D8 IIC2A
AD7 AD6 AD5 AD4 AD3 AD2 AD1 0
0x18D9 IIC2F
MULT ICR
0x18DA IIC2C1
IICEN IICIE MST TX TXAK RSTA 0 0
0x18DB IIC2S
TCF IAAS BUSY ARBL 0 SRW IICIF RXAK
0x18DC IIC2D
DATA
0x18DD IIC2C2
GCAEN ADEXT 0 0 0 AD10 AD9 AD8
0x18DE–
0x18FF
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Table 4-4. MSCAN Foreground Receive and Transmit Buffer Layouts — Extended Mapping Shown
(Sheet 1 of 2)
0x18A0 CANRIDR0
ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21
0x18A1 CANRIDR1
ID20 ID19 ID18 SRR
(1)
IDE
(1)
ID17 ID16 ID15
0x18A2 CANRIDR2
ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7
0x18A3 CANRIDR3
ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR
2
0x18A4 –
0x18AB
CANRDSR0 –
CANRDSR7
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0x18AC CANRDLR
— — — — DLC3 DLC2 DLC1 DLC0
0x18AD Reserved
— — — — — — — —
0x18AE CANRTSRH
TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8
0x18AF CANRTSRL
TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0
0x18B0 CANTIDR0
ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21
0x18B1 CANTIDR1
ID20 ID19 ID18 SRR
(3)
IDE
(1)
ID17 ID16 ID15
0x18B2 CANTIDR2
ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7
Table 4-3. High-Page Register Summary (Sheet 5 of 5)
Address Register Name Bit 7 654321Bit 0