Datasheet

Chapter 7 Central Processor Unit (S08CPUV3)
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
106 Freescale Semiconductor
CLC Clear Carry Bit (C ← 0) INH 98 1 p –11– –––0
CLI Clear Interrupt Mask Bit (I ← 0) INH 9A 1 p –11– 0–––
CLR opr8a
CLRA
CLRX
CLRH
CLR oprx8,X
CLR ,X
CLR oprx8,SP
Clear M ← $00
A ← $00
X ← $00
H ← $00
M ← $00
M ← $00
M ← $00
DIR
INH
INH
INH
IX1
IX
SP1
3F
4F
5F
8C
6F
7F
9E 6F
dd
ff
ff
5
1
1
1
5
4
6
rfwpp
p
p
p
rfwpp
rfwp
prfwpp
011– –01–
CMP #opr8i
CMP opr8a
CMP opr16a
CMP oprx16,X
CMP oprx8,X
CMP ,X
CMP oprx16,SP
CMP oprx8,SP
Compare Accumulator with Memory
A – M
(CCR Updated But Operands Not Changed)
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A1
B1
C1
D1
E1
F1
9E D1
9E E1
ii
dd
hh
ll
ee
ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
pp
rpp
prpp
prpp
rpp
rfp
pprpp
prpp
 11 ––  
COM opr8a
COMA
COMX
COM oprx8,X
COM ,X
COM oprx8,SP
Complement M ← (M
)= $FF – (M)
(One’s Complement) A ← (A
) = $FF – (A)
X ← (X
) = $FF – (X)
M ← (M
) = $FF – (M)
M ← (M
) = $FF – (M)
M ← (M
) = $FF – (M)
DIR
INH
INH
IX1
IX
SP1
33
43
53
63
73
9E 63
dd
ff
ff
5
1
1
5
4
6
rfwpp
p
p
rfwpp
rfwp
prfwpp
011– –  1
CPHX opr16a
CPHX #opr16i
CPHX opr8a
CPHX oprx8,SP
Compare Index Register (H:X) with Memory
(H:X) – (M:M + $0001)
(CCR Updated But Operands Not Changed)
EXT
IMM
DIR
SP1
3E
65
75
9E F3
hh ll
jj kk
dd
ff
6
3
5
6
prrfpp
ppp
rrfpp
prrfpp
 11 ––  
CPX #opr8i
CPX opr8a
CPX opr16a
CPX oprx16,X
CPX oprx8,X
CPX ,X
CPX oprx16,SP
CPX oprx8,SP
Compare X (Index Register Low) with
Memory
X – M
(CCR Updated But Operands Not Changed)
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A3
B3
C3
D3
E3
F3
9E D3
9E E3
ii
dd
hh ll
ee ff
ff
ee
ff
ff
2
3
4
4
3
3
5
4
pp
rpp
prpp
prpp
rpp
rfp
pprpp
prpp
 11 ––
 
DAA
Decimal Adjust Accumulator
After ADD or ADC of BCD Values
INH 72 1 p U11– –  
DBNZ opr8a,rel
DBNZA rel
DBNZX rel
DBNZ oprx8,X,rel
DBNZ ,X,rel
DBNZ oprx8,SP,rel
Decrement A, X, or M and Branch if Not Zero
(if (result) ≠ 0)
DBNZX Affects X Not H
DIR
INH
INH
IX1
IX
SP1
3B
4B
5B
6B
7B
9E 6B
dd rr
rr
rr
ff rr
rr
ff rr
7
4
4
7
6
8
rfwpppp
fppp
fppp
rfwpppp
rfwppp
prfwpppp
–11– ––––
DEC opr8a
DECA
DECX
DEC oprx8,X
DEC ,X
DEC oprx8,SP
Decrement M ← (M) – $01
A ← (A) – $01
X ← (X) – $01
M ←
(M) – $
01
M ← (M) – $01
M ← (M) – $01
DIR
INH
INH
IX1
IX
SP1
3A
4A
5A
6A
7A
9E 6A
dd
ff
ff
5
1
1
5
4
6
rfwpp
p
p
rfwpp
rfwp
prfwpp
 11 ––  –
Table 7-2. Instruction Set Summary (Sheet 4 of 9)
Source
Form
Operation
Address
Mode
Object Code
Cycles
Cyc-by-Cyc
Details
Affect
on CCR
V 1 1 HI N Z C