Datasheet

Chapter 6 Parallel Input/Output
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 101
76543210
R
PTGD7 PTGD6 PTGD5 PTGD4 PTGD3 PTGD2 PTGD1 PTGD0
W
Reset00000000
Figure 6-33. Port PTG Data Register (PTGD)
Table 6-25. PTGD Field Descriptions
Field Description
7:0
PTGD[7:0]
Port PTG Data Register Bits — For port G pins that are inputs, reads return the logic level on the pin. For port
G pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port G pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTGD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
76543210
R
PTGPE7 PTGPE6 PTGPE5 PTGPE4 PTGPE3 PTGPE2 PTGPE1 PTGPE0
W
Reset00000000
Figure 6-34. Pullup Enable for Port G (PTGPE)
Table 6-26. PTGPE Field Descriptions
Field Description
7:0
PTGPE[7:0]
Pullup Enable for Port G Bits — For port G pins that are inputs, these read/write control bits determine whether
internal pullup devices are enabled. For port G pins that are configured as outputs, these bits are ignored and
the internal pullup devices are disabled.
0 Internal pullup device disabled.
1 Internal pullup device enabled.