Datasheet
Analog-to-Digital Converter (S08ATDV3)
MC9S08GB60A Data Sheet, Rev. 2
234 Freescale Semiconductor
14.6.1 ATD Control (ATDC)
Writes to the ATD control register will abort the current conversion, but will not start a new conversion.
76543210
R
ATDPU DJM RES8 SGN PRS
W
Reset00000000
Figure 14-5. ATD Control Register (ATD1C)
Table 14-3. ATD1C Field Descriptions
Field Description
7
ATD PU
ATD Power Up — This bit provides program on/off control over the ATD, reducing power consumption when the
ATD is not being used. When cleared, the ATDPU bit aborts any conversion in progress.
0 Disable the ATD and enter a low-power state.
1 ATD functionality.
6
DJM
Data Justification Mode — This bit determines how the 10-bit conversion result data maps onto the ATD result
register bits. When RES8 is set, bit DJM has no effect and the 8-bit result is always located in ATD1RH.
See Section 14.6.3, “ATD Result Data (ATD1RH, ATD1RL),” for de tails.
The effect of the DJM bit on the result is shown in Tabl e 14 -4.
0 Result register data is left justified.
1 Result register data is right justified.
5
RES8
ATD Resolution Select — This bit determines the resolution of the ATD converter, 8-bits or 10-bits. The ATD
converter has the accuracy of a 10-bit converter. However, if 8-bit compatibility is required, selecting 8-bit
resolution will map result data bits 9-2 onto ATD1RH bits 7-0
.
The effect of the RES8 bit on the result is shown in Table 14-4.
0 10-bit resolution selected.
1 8-bit resolution selected.
4
SGN
Signed Result Select — This bit determines whether the result will be signed or unsigned data. Signed data is
represented as 2’s complement data and is achieved by complementing the MSB of the result. Signed data mode
can be used only when the result is left justified (DJM = 0) and is not available for right-justified mode (DJM = 1).
When a signed result is selected, the range for conversions becomes –512 (0x200) to 511 (0x1FF) for 10-bit
resolution and –128 (0x80) to 127 (0x7F) for 8-bit resolution.
The effect of the SGN bit on the result is shown in Ta bl e 14- 4.
0 Left justified result data is unsigned.
1 Left justified result data is signed.
3:0
PRS
Prescaler Rate Select — This field of bits determines the prescaled factor for the ATD conversion clock.
Ta bl e 14 -5 illustrates the divide-by operation and the appropriate range of bus clock frequencies.