Datasheet

Parallel Input/Output
MC9S08GT16A/GT8A Data Sheet, Rev. 1
98 Freescale Semiconductor
76543210
R
0000
PTGSE3 PTGSE2 PTGSE1 PTGSE0
W
Reset 00000000
Figure 6-30. Slew Rate Control Enable for Port G (PTGSE)
Table 6-23. PTGSE Field Descriptions
Field Description
3:0
PTGSE[3:0]
Slew Rate Control Enable for Port G Bits — For port G pins that are outputs, these read/write control bits
determine whether the slew rate controlled outputs are enabled. For port G pins that are configured as inputs,
these bits are ignored.
0 Slew rate control disabled.
1 Slew rate control enabled.
76543210
R
0000
PTGDD3 PTGDD2 PTGDD1
PTGDD0
Note
(1)
1
Although PTGDD0 is implemented, this bit actually has no effect on the operation of PTG0/BKGD.
W
Reset 00000000
Figure 6-31. Data Direction for Port G (PTGDD)
Table 6-24. PTGDD Field Descriptions
Field Description
3:0
PTGDD[3:0]
Data Direction for Port G Bits — These read/write bits control the direction of port G pins and what is read for
PTGD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn.