Datasheet

Analog-to-Digital Converter (S08ATDV3)
MC9S08GB60A Data Sheet, Rev. 2
238 Freescale Semiconductor
Figure 14-7. Left-Justified Mode
For right-justified mode, result data bits 9 and 8 map onto bits 1 and 0 of ATD1RH, result data bits 7–0
map onto ATD1RL bits 7–0, where bit 1 of ATD1RH is the most significant bit (MSB).
Figure 14-8. Right-Justified Mode
The ATD 10-bit conversion results are stored in two 8-bit result registers, ATD1RH and ATD1RL. The
result data is formatted either left or right justified where the format is selected using the DJM control bit
in the ATD1C register. The 10-bit result data is mapped either between ATD1RH bits 7–0 and ATD1RL
bits 7–6 (left justified), or ATD1RH bits 1–0 and ATD1RL bits 7–0 (right justified).
For 8-bit conversions, the 8-bit result is always located in ATD1RH bits 7–0, and the ATD1RL bits read
0. For 10-bit conversions, the six unused bits always read 0.
The ATD1RH and ATD1RL registers are read-only.
14.6.4 ATD Pin Enable (ATD1PE)
The ATD pin enable register allows the pins dedicated to the ATD module to be configured for ATD usage.
A write to this register will abort the current conversion but will not initiate a new conversion. If the
ATDPEx bit is 0 (disabled for ATD usage) but the corresponding analog input channel is selected via the
ATDCH bits, the ATD will not convert the analog input but will instead convert V
REFL
placing zeroes in
the ATD result registers.
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
9 0
ATD1RH ATD1RL
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
9 0
ATD1RH ATD1RL
76543210
R
ATDPE7 ATDPE6 ATDPE5 ATDPE4 ATDPE3 ATDPE2 ATDPE1 ATDPE0
W
Reset00000000
Figure 14-9. ATD Pin Enable Register (ATD1PE)
Table 14-8. ATD1PE Field Descriptions
Field Description
7
ATDPE[7:0]
ATD Pin 7–0 Enables
0 Pin disabled for ATD usage.
1 Pin enabled for ATD usage.
RESULT
RESULT