Datasheet

Internal Clock Generator (S08ICGV2)
MC9S08GB60A Data Sheet, Rev. 2
128 Freescale Semiconductor
7.5.6 ICG Trim Register (ICGTRM)
76543210
R
FLT
W
Reset11000000
= Unimplemented or Reserved
Figure 7-17. ICG Upper Filter Register (ICGFLTL)
Table 7-11. ICGFLTL Field Descriptions
Field Description
7:0
FLT
Filter Value — The FLT bits indicate the current filter value, which controls the DCO frequency. The FLT bits are
read only except when the CLKS bits are programmed to self-clocked mode (CLKS = 00). In self-clocked mode,
any write to ICGFLTU updates the current 12-bit filter value. Writes to the ICGFLTU register will not affect FLT if
a previous latch sequence is not complete.
76543210
R
TRIM
W
POR:10000000
Reset:uuuuuuuu
= Unimplemented or Reserved u = Unaffected by MCU reset
Figure 7-18. ICG Trim Register (ICGTRM)
Table 7-12. ICGTRM Field Descriptions
Field Description
7:0
TRIM
ICG Trim Setting — The TRIM bits control the internal reference generator frequency. They allow a ± 25%
adjustment of the nominal (POR) period. The bit’s effect on period is binary weighted (i.e., bit 1 will adjust twice
as much as changing bit 0). Increasing the binary value in TRIM will increase the period and decreasing the value
will decrease the period.