Datasheet

Appendix A Electrical Characteristics
MC9S08GB60A Data Sheet, Rev. 2
276 Freescale Semiconductor
A.9.1 Control Timing
Figure A-11. Reset Timing
Figure A-12. Active Background Debug Mode Latch Timing
Table A-10. Control Timing
Parameter Symbol Min Typical Max Unit
Bus frequency (t
cyc
= 1/f
Bus
)f
Bus
dc — 20 MHz
Real-time interrupt internal oscillator period
t
RTI
700 1300 μs
External reset pulse width
1
1
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
t
extrst
1.5 x
f
Self_reset
—ns
Reset low drive
2
2
When any reset is initiated, internal circuitry drives the reset pin low for about 34 cycles of f
Self_reset
and then samples the level
on the reset pin about 38 cycles later to distinguish external reset requests from internal requests.
t
rstdrv
34 x
f
Self_reset
—ns
Active background debug mode latch setup time
t
MSSU
25 — ns
Active background debug mode latch hold time
t
MSH
25 — ns
IRQ pulse width
3
3
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
t
ILIH
1.5 x t
cyc
—ns
Port rise and fall time (load = 50 pF)
4
Slew rate control disabled
Slew rate control enabled
4
Timing is shown with respect to 20% V
DD
and 80% V
DD
levels. Temperature range –40°C to 85°C.
t
Rise
, t
Fall
—
—
3
30
ns
t
extrst
RESET PIN
BKGD/MS
RESET
t
MSSU
t
MSH