Datasheet

Chapter 2 Pins and Connections
MC9S08GB60A Data Sheet, Rev. 2
32 Freescale Semiconductor
2.3.6 Signal Properties Summary
Table 2-2 summarizes I/O pin characteristics. These characteristics are determined by the way the
common pin interfaces are hardwired to internal circuits.
Table 2-2. Signal Properties
Pin
Name
Dir
High Current
Pin
Output
Slew
1
Pull-Up
2
Comments
V
DD
———
V
SS
———
The 48-pin QFN package has two V
SS
pins — V
SS1
and V
SS2
.
V
DDAD
———
V
SSAD
———
V
REFH
———
V
REFL
———
RESET
I/O Y N Y Pin contains integrated pullup.
IRQ
I— — Y
IRQPE must be set to enable IRQ function.
IRQ does not have a clamp diode to V
DD
. IRQ should
not be driven above V
DD
.
Pullup/pulldown active when IRQ pin function
enabled. Pullup forced on when IRQ enabled for
falling edges; pulldown forced on when IRQ enabled
for rising edges.
PTA0/KBI1P0 I/O N SWC SWC
PTA1/KBI1P1 I/O N SWC SWC
PTA2/KBI1P2 I/O N SWC SWC
PTA3/KBI1P3 I/O N SWC SWC
PTA4/KBI1P4 I/O N SWC SWC
Pullup/pulldown active when KBI pin function
enabled. Pullup forced on when KBI1Px enabled for
falling edges; pulldown forced on when KBI1Px
enabled for rising edges.
PTA5/KBI1P5 I/O N SWC SWC
PTA6/KBI1P6 I/O N SWC SWC
PTA7/KBI1P7 I/O N SWC SWC
PTB0/AD1P0 I/O N SWC SWC
PTB1/AD1P1 I/O N SWC SWC
PTB2/AD1P2 I/O N SWC SWC
PTB3/AD1P3 I/O N SWC SWC
PTB4/AD1P4 I/O N SWC SWC
PTB5/AD1P5 I/O N SWC SWC
PTB6/AD1P6 I/O N SWC SWC
PTB7/AD1P7 I/O N SWC SWC
PTC0/TxD2 I/O Y SWC SWC
When pin is configured for SCI function, pin is
configured for partial output drive.
PTC1/RxD2 I/O Y SWC SWC
PTC2/SDA1 I/O Y SWC SWC
PTC3/SCL1 I/O Y SWC SWC
PTC4 I/O Y SWC SWC
PTC5 I/O Y SWC SWC Not available on 42-pin package
PTC6 I/O Y SWC SWC Not available on 42-pin package