Datasheet

Chapter 3 Modes of Operation
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 37
when the CPU executes a STOP instruction, the MCU will not enter any of the stop modes and an illegal
opcode reset is forced. The stop modes are selected by setting the appropriate bits in SPMSC2.
Table 3-1 summarizes the behavior of the MCU in each of the stop modes.
3.6.1 Stop1 Mode
The stop1 mode provides the lowest possible standby power consumption by causing the internal circuitry
of the MCU to be powered down. Stop1 can be entered only if the LVD circuit is not enabled in stop modes
(either LVDE or LVDSE not set).
When the MCU is in stop1 mode, all internal circuits that are powered from the voltage regulator are turned
off. The voltage regulator is in a low-power standby state, as is the ATD.
Exit from stop1 is performed by asserting either of the wake-up pins on the MCU: RESET or IRQ. IRQ is
always an active low input when the MCU is in stop1, regardless of how it was configured before entering
stop1.
Entering stop1 mode automatically asserts LVD. Stop1 cannot be exited until V
DD
> V
LVDH/L
rising (V
DD
must rise above the LVI rearm voltage).
Upon wake-up from stop1 mode, the MCU will start up as from a power-on reset (POR). The CPU will
take the reset vector.
3.6.2 Stop2 Mode
The stop2 mode provides very low standby power consumption and maintains the contents of RAM and
the current state of all of the I/O pins. Stop2 can be entered only if the LVD circuit is not enabled in stop
modes (either LVDE or LVDSE not set).
Before entering stop2 mode, the user must save the contents of the I/O port registers, as well as any other
memory-mapped registers they want to restore after exit of stop2, to locations in RAM. Upon exit of stop2,
these values can be restored by user software before pin latches are opened.
When the MCU is in stop2 mode, all internal circuits that are powered from the voltage regulator are turned
off, except for the RAM. The voltage regulator is in a low-power standby state, as is the ATD. Upon entry
Table 3-1. Stop Mode Behavior
Mode PDC PPDC
CPU, Digital
Peripherals,
Flash
RAM ICG ATD Regulator I/O Pins RTI
Stop1 1 0 Off Off Off Disabled
1
1
Either ATD stop mode or power-down mode depending on the state of ATDPU.
Off Reset Off
Stop2 1 1 Off Standby Off Disabled Standby States held Optionally on
Stop3 0 Don’t
care
Standby Standby Off
2
2
Crystal oscillator can be configured to run in stop3. Please see the ICG registers.
Disabled Standby States held Optionally on