Datasheet

MC9S08GB60A Data Sheet, Rev. 2

6 Freescale Semiconductor

Revision History

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be the most current. Your printed copy may be an earlier revision. To verify you have the latest information

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The following revision history table summarizes changes contained in this document.

Revision

Number

Revision

Date

Description of Changes

1.00 07/14/2005 Initial public release.

1.01 09/04/2007

Added a footnote to RTI of Table 3.2; Added RTI description to Section 3.5.6;

Added a sentence "If active BDM mode is enabled in stop3, the internal RTI

clock is not available." to the Section 5.7 Real Time Interrupt.

1.02 02/25/2008

Changed the Maximun Low Power of FBE and FEE in Table A - 9 to 10 MHz.

Changed the Title of Ta ble 1 3- 2 from “IIC1A Register Field Descriptions” to

“IIC1F Register Field Descriptions”

2 7/30/2008

Added 42-pin SDIP information.

Changed “However, when HGO=0, the maximum frequency is 8 MHz in FEE

and FBE modes.” to “However, when HGO=0, the maximum frequency is

10 MHz in FEE and FBE modes.” in Appendix B5.

Updated the “How to reach us” at backpage.

This product incorporates SuperFlash

technology licensed from SST.

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