Datasheet

Chapter 4 Memory
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 51
to program the entire array through the single-wire background debug interface. Because no special
voltages are needed for flash erase and programming operations, in-application programming is also
possible through other software-controlled communication paths. For a more detailed discussion of
in-circuit and in-application programming, refer to the HCS08 Family Reference Manual, Volume I,
Freescale Semiconductor document order number HCS08RMv1/D.
4.4.1 Features
Features of the flash memory include:
•Flash Size
— MC9S08GB60A/MC9S08GT60A — 61268 bytes (120 pages of 512 bytes each)
— MC9S08GB32A/MC9S08GT32A— 32768 bytes (64 pages of 512 bytes each)
• Single power supply program and erase
• Command interface for fast program and erase operation
• Up to 100,000 program/erase cycles at typical voltage and temperature
• Flexible block protection
• Security feature for flash and RAM
• Auto power-down for low-frequency read accesses
4.4.2 Program and Erase Times
Before any program or erase command can be accepted, the flash clock divider register (FCDIV) must be
written to set the internal clock for the flash module to a frequency (f
FCLK
) between 150 kHz and 200 kHz
(see Table 4.6.1). This register can be written only once, so normally this write is done during reset
initialization. FCDIV cannot be written if the access error flag, FACCERR in FSTAT, is set. The user must
ensure that FACCERR is not set before writing to the FCDIV register. One period of the resulting clock
(1/f
FCLK
) is used by the command processor to time program and erase pulses. An integer number of these
timing pulses is used by the command processor to complete a program or erase command.
Table 4-5 shows program and erase times. The bus clock frequency and FCDIV determine the frequency
of FCLK (f
FCLK
). The time for one cycle of FCLK is t
FCLK
=1/f
FCLK
. The times are shown as a number
of cycles of FCLK and as an absolute time for the case where t
FCLK
=5μs. Program and erase times
shown include overhead for the command state machine and enabling and disabling of program and erase
voltages.
Table 4-5. Program and Erase Times
Parameter Cycles of FCLK Time if FCLK = 200 kHz
Byte program 9 45 μs
Byte program (burst) 4
20 μs
1
1
Excluding start/end overhead
Page erase 4000 20 ms
Mass erase 20,000 100 ms