Datasheet

Chapter 6 Parallel Input/Output
MC9S08GB60A Data Sheet, Rev. 2
102 Freescale Semiconductor
76543210
R
PTGSE7 PTGSE6 PTGSE5 PTGSE4 PTGSE3 PTGSE2 PTGSE1 PTGSE0
W
Reset00000000
Figure 6-35. Slew Rate Control Enable for Port G (PTGSE)
Table 6-27. PTGSE Field Descriptions
Field Description
7:0
PTGSE[7:0]
Slew Rate Control Enable for Port G Bits — For port G pins that are outputs, these read/write control bits
determine whether the slew rate controlled outputs are enabled. For port G pins that are configured as inputs,
these bits are ignored.
0 Slew rate control disabled.
1 Slew rate control enabled.
76543210
R
PTGDD7 PTGDD6 PTGDD5 PTGDD4 PTGDD3 PTGDD2 PTGDD1 PTGDD0
W
Reset00000000
Figure 6-36. Data Direction for Port G (PTGDD)
Table 6-28. PTGDD Field Descriptions
Field Description
7:0
PTGDD[7:0]
Data Direction for Port G Bits — These read/write bits control the direction of port G pins and what is read for
PTGD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn.