Datasheet

Internal Clock Generator (S08ICGV2)
MC9S08GB60A Data Sheet, Rev. 2
110 Freescale Semiconductor
In this state, the FLL loop is open. The DCO is on, and the output clock signal ICGOUT frequency is given
by f
ICGDCLK
/ R. The ICGDCLK frequency can be varied from 8 MHz to 40 MHz by writing a new value
into the filter registers (ICGFLTU and ICGFLTL). This is the only mode in which the filter registers can
be written.
If this mode is entered due to a reset, f
ICGDCLK
will default to f
Self_reset
which is nominally 8 MHz. If this
mode is entered from FLL engaged internal, f
ICGDCLK
will maintain the previous frequency. If this mode
is entered from FLL engaged external (either by programming CLKS or due to a loss of external reference
clock), f
ICGDCLK
will maintain the previous frequency, but ICGOUT will double if the FLL was unlocked.
If this mode is entered from off mode, f
ICGDCLK
will be equal to the frequency of ICGDCLK before
entering off mode. If CLKS bits are set to 01 or 11 coming out of the Off state, the ICG enters this mode
until ICGDCLK is stable as determined by the DCOS bit. Once ICGDCLK is considered stable, the ICG
automatically closes the loop by switching to FLL engaged (internal or external) as selected by the CLKS
bits.
Figure 7-6. Detailed Frequency-Locked Loop Block Diagram
REFERENCE
DIVIDER (/7)
RFD
CLKST
SUBTRACTOR
LOOP
FILTER
DIGITALLY
CONTROLLED
OSCILLATOR
CLOCK
ICGOUT
ICG2DCLK
RESET AND
INTERRUPT
IRQ
FLL ANALOG
SELECT
CIRCUIT
LOLS
PULSE
COUNTER
MFD
FREQUENCY-
ICGERCLK
LOCS
LOCK AND
DETECTOR
LOCK
CONTROL
LOLRE LOCRE
RESET
REDUCED
FREQUENCY
DIVIDER (R)
LOSS OF CLOCK
ICGIF
ERCS
ICGDCLK
LOOP (FLL)
DIGITAL
FLT
COUNTER ENABLE
LOCKED
OVERFLOW
1x
2x
ICGIRCLK
CLKST
DCOS
RANGE
RANGE
CLKS
LOCD